An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.
Chung-Shiang WuKai-Chun LinYi-Ping KuoPo-Hung ChenYuan-Hua ChuWei HwangPublished in: ISCAS (2015)
Keyphrases
- power consumption
- low power
- power management
- energy efficiency
- low voltage
- high power
- power saving
- battery life
- dynamic power management
- mixed signal
- energy dissipation
- single chip
- digital signal processing
- low cost
- image sensor
- vlsi architecture
- low power consumption
- energy saving
- high speed
- power dissipation
- gate array
- data center
- logic circuits
- vlsi circuits
- ultra low power
- cmos technology
- signal processing