Ping-Lin Yang

Publication Activity (10 Years)

Years Active: 2013-2018
Publications (10 Years): 3

Top Topics

Cmos Technology

Subband Decomposition

Laparoscopic Surgery

Power Dissipation

Top Venues

Publications

Ping-Lin Yang, Malgorzata Marek-Sadowska
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Ping-Lin Yang, Malgorzata Marek-Sadowska
A fast, fully verifiable, and hardware predictable ASIC design methodology. ICCD (2016)
Ping-Lin Yang, Malgorzata Marek-Sadowska
Making split-fabrication more secure. ICCAD (2016)
Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC (2015)
Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC (2014)
Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC (2014)
Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang
A 4-GHz universal high-frequency on-chip testing platform for IP validation. VTS (2014)
Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong
per MB. CICC (2013)