Malgorzata Marek-Sadowska

ORCID

Publication Activity (10 Years)

Years Active: 1983-2023
Publications (10 Years): 9

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

ISPD

ISQED

ICCAD

Publications

Malgorzata Marek-Sadowska
ISPD 2023 Lifetime Achievement Award Bio. ISPD (2023)
Ali Abbasinasab, Malgorzata Marek-Sadowska
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. ACM Great Lakes Symposium on VLSI (2019)
Ping-Lin Yang, Malgorzata Marek-Sadowska
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Ali Abbasinasab, Malgorzata Marek-Sadowska
RAIN: a tool for reliability assessment of interconnect networks - physics to software. DAC (2018)
Zhong Guan, Malgorzata Marek-Sadowska
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation. ICCAD (2016)
Ping-Lin Yang, Malgorzata Marek-Sadowska
A fast, fully verifiable, and hardware predictable ASIC design methodology. ICCD (2016)
Zhong Guan, Malgorzata Marek-Sadowska
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Ping-Lin Yang, Malgorzata Marek-Sadowska
Making split-fabrication more secure. ICCAD (2016)
Zhong Guan, Malgorzata Marek-Sadowska
AFD-based method for signal line EM reliability evaluation. ISQED (2016)
Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Li-C. Wang, Malgorzata Marek-Sadowska
Machine Learning in Simulation-Based Analysis. ISPD (2015)
Ali Abbasinasab, Malgorzata Marek-Sadowska
Blech Effect in Interconnects: Applications and Design Guidelines. ISPD (2015)
Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Vivek S. Nandakumar, Malgorzata Marek-Sadowska
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. DAC (2014)
Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
Statistical analysis of process variation induced SRAM electromigration degradation. ISQED (2014)
Vivek S. Nandakumar, Malgorzata Marek-Sadowska
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. IEEE Comput. Archit. Lett. 13 (2) (2014)
Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Di-An Li, Malgorzata Marek-Sadowska
Estimating true worst currents for power grid electromigration analysis. ISQED (2014)
Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD (2013)
Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
SRAM bit-line electromigration mechanism and its prevention scheme. ISQED (2013)
Xiang Qiu, Malgorzata Marek-Sadowska
Routing Challenges for Designs With Super High Pin Density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED (2012)
Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. ISQED (2012)
Xiang Qiu, Malgorzata Marek-Sadowska
Can pin access limit the footprint scaling? DAC (2012)
Vivek S. Nandakumar, Malgorzata Marek-Sadowska
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska
Rapid layout pattern classification. ASP-DAC (2011)
Aida Todri, Malgorzata Marek-Sadowska
Power Delivery for Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Vivek S. Nandakumar, Malgorzata Marek-Sadowska
Layout effects in fine grain 3D integrated regular microprocessor blocks. DAC (2011)
Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska
Metrics for characterizing machine learning-based hotspot detection methods. ISQED (2011)
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Di-An Li, Malgorzata Marek-Sadowska
Variation-aware electromigration analysis of power/ground networks. ICCAD (2011)
Aida Todri, Malgorzata Marek-Sadowska
Reliability Analysis and Optimization of Power-Gated ICs. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Malgorzata Marek-Sadowska
On old and new routing problems. ISPD (2011)
Vivek S. Nandakumar, Malgorzata Marek-Sadowska
Low power, high throughput network-on-chip fabric for 3D multicore processors. ICCD (2011)
Di-An Li, Malgorzata Marek-Sadowska, Bill Lee
On-chip em-sensitive interconnect structures. SLIP (2010)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Performance study of VeSFET-based, high-density regular circuits. ISPD (2010)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska
Statistical static timing analysis flow for transistor level macros in a microprocessor. ISQED (2010)
Aida Todri, Malgorzata Marek-Sadowska
Electromigration study of power-gated grids. ISLPED (2009)
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron
A study of decoupling capacitor effectiveness in power and ground grid networks. ISQED (2009)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Transistor-level layout of high-density regular circuits. ISPD (2009)
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED (2008)
Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya
Power supply noise aware workload assignment for multi-core systems. ICCAD (2008)
Nilesh A. Modi, Malgorzata Marek-Sadowska
ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ICCD (2008)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
Is there always performance overhead for regular fabric? ICCD (2008)
Aida Todri, Malgorzata Marek-Sadowska
A study of reliability issues in clock distribution networks. ICCD (2008)
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Timing analysis considering IR drop waveforms in power gating designs. ICCD (2008)
Hailin Jiang, Malgorzata Marek-Sadowska
Power gating scheduling for power/ground noise reduction. DAC (2008)
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang
Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD (2007)
Hailin Jiang, Malgorzata Marek-Sadowska
Power-Gating Aware Floorplanning. ISQED (2007)
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC (2007)
Chao-Yang Yeh, Malgorzata Marek-Sadowska
Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Engineering change using spare cells with constant insertion. ICCAD (2007)
Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED (2007)
Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
OPC-Free and Minimally Irregular IC Design Style. DAC (2007)
Yajun Ran, Malgorzata Marek-Sadowska
Designing via-configurable logic blocks for regular fabric. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
Delay Fault Diagnosis for Non-Robust Test. ISQED (2006)
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC (2006)
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
Analysis of Process Variation's Effect on SRAM's Read Stability. ISQED (2006)
Yajun Ran, Malgorzata Marek-Sadowska
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. Very Large Scale Integr. Syst. 14 (9) (2006)
Qinghua Liu, Malgorzata Marek-Sadowska
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Hailin Jiang, Malgorzata Marek-Sadowska
Power/ground supply network optimization for power-gating. ICCD (2006)
Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska
mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD (2005)
Qinghua Liu, Malgorzata Marek-Sadowska
A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI (2005)
Bo Hu, Malgorzata Marek-Sadowska
Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (8) (2005)
Chao-Yang Yeh, Malgorzata Marek-Sadowska
Skew-programmable clock design for FPGA and skew-aware placement. FPGA (2005)
Qinghua Liu, Malgorzata Marek-Sadowska
A study of netlist structure and placement efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska
Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI (2005)
Yajun Ran, Malgorzata Marek-Sadowska
Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD (2005)
Chao-Yang Yeh, Malgorzata Marek-Sadowska
Timing-aware power noise reduction in layout. ICCAD (2005)
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
Benefits and Costs of Power-Gating Technique. ICCD (2005)
Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Kai Wang, Malgorzata Marek-Sadowska
On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (3) (2005)
Qinghua Liu, Malgorzata Marek-Sadowska
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD (2005)
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED (2005)
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Qinghua Liu, Malgorzata Marek-Sadowska
Wire length prediction-based technology mapping and fanout optimization. ISPD (2005)
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53 (9) (2004)
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Delay Fault Diagnosis Using Timing Information. ISQED (2004)
Qinghua Liu, Malgorzata Marek-Sadowska
Pre-layout wire length and congestion estimation. DAC (2004)
Yajun Ran, Malgorzata Marek-Sadowska
The Magic of a Via-Configurable Regular Fabric. ICCD (2004)
Kai Wang, Malgorzata Marek-Sadowska
Buffer sizing for clock power minimization subject to general skew constraints. DAC (2004)
Chao-Yang Yeh, Malgorzata Marek-Sadowska
Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. 12 (10) (2004)
Kai Wang, Malgorzata Marek-Sadowska
Clock network sizing via sequential linear programming with time-domain analysis. ISPD (2004)
Yajun Ran, Malgorzata Marek-Sadowska
An integrated design flow for a via-configurable gate array. ICCAD (2004)
Kai Wang, Malgorzata Marek-Sadowska
Potential Slack Budgeting with Clock Skew Optimization. ICCD (2004)
Qinghua Liu, Malgorzata Marek-Sadowska
A study of netlist structure and placement efficiency. ISPD (2004)
Bo Hu, Malgorzata Marek-Sadowska
Fine granularity clustering-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
Individual wire-length prediction with application to timing-driven placement. IEEE Trans. Very Large Scale Integr. Syst. 12 (10) (2004)
Bo Hu, Malgorzata Marek-Sadowska
Multilevel expansion-based VLSI placement with blockages. ICCAD (2004)
Yajun Ran, Malgorzata Marek-Sadowska
Designing a via-configurable regular fabric. CICC (2004)
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Diagnosis of Hold Time Defects. ICCD (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

Malgorzata Marek-Sadowska