Skew-programmable clock design for FPGA and skew-aware placement.

Chao-Yang Yeh Malgorzata Marek-Sadowska

Published in: FPGA (2005)

Keyphrases

single chip
low cost
high speed
real time
hardware design
building blocks
low power
database
case study
general purpose
verilog hdl
gate array
hardware architecture
design tools
design decisions
computer aided
software architecture
software systems
design process
genetic algorithm