Andrzej Pfitzner

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 5

Top Topics

Schottky Barrier

Storage Capacity

Gaussian Mixture

Top Venues

Publications

Bartosz Dec, Andrzej Pfitzner
Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology. MIXDES (2024)
Mikolaj Palgan, Andrzej Pfitzner
Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology. MIXDES (2018)
Bartosz Dec, Andrzej Pfitzner
Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology. MIXDES (2018)
Andrzej Pfitzner, Beata Kowalska
Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET). MIXDES (2016)
Michal Staniewski, Andrzej Pfitzner
Compact DC model of a JVeSFET transistor with reduced number of empirical parameters. MIXDES (2015)
Andrzej Pfitzner
Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET). MIXDES (2014)
Michal Staniewski, Andrzej Pfitzner
Usefulness of VeSTIC devices for low-noise and radiation hard 3D integrated circuits. MIXDES (2014)
Andrzej Pfitzner
Vertical Slit Transistor based Integrated Circuits (VeSTICs). DDECS (2012)
Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel
Adder Circuits with Transistors using Independently Controlled Gates. ISCAS (2009)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
Is there always performance overhead for regular fabric? ICCD (2008)
Adam Jarosz, Andrzej Pfitzner
Evaluation of parasitic capacitances for interconnection buses crossing in different layers. Microelectron. Reliab. 45 (3-4) (2005)