A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures.
Vivek S. NandakumarMalgorzata Marek-SadowskaPublished in: IEEE J. Emerg. Sel. Topics Circuits Syst. (2012)
Keyphrases
- low energy
- network on chip
- routing algorithm
- network simulator
- electron microscopy
- cluster head
- multi processor
- data transfer
- power dissipation
- coarse grained
- protein folding
- wireless sensor networks
- three dimensional
- interconnection networks
- fine grained
- routing problem
- ad hoc networks
- shortest path
- multi hop
- energy efficient
- data flow
- routing protocol
- energy consumption
- sensor networks
- real time