Luca Macchiarulo

Publication Activity (10 Years)

Years Active: 1998-2011
Publications (10 Years): 0

Publications

Xin Gao, Luca Macchiarulo
A jumper insertion algorithm under antenna ratio and timing constraints. ICCAD (2011)
Xin Gao, Luca Macchiarulo
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. DATE (2010)
Wansuree Massagram, Noah Hafner, Mingqi Chen, Luca Macchiarulo, Victor Lubecke, Olga Boric-Lubecke
Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC. IEEE Trans. Biomed. Circuits Syst. 4 (1) (2010)
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni
A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Mario R. Casu, Luca Macchiarulo
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. Electron. Notes Theor. Comput. Sci. 245 (2009)
Mario R. Casu, Luca Macchiarulo
Adaptive Latency-Insensitive Protocols. IEEE Des. Test Comput. 24 (5) (2007)
Sergio Tota, Mario R. Casu, Luca Macchiarulo
Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI (2006)
Luca Macchiarulo
Using Existing Digital Tools for Efficient Metabolic Pathway Simulations. EMBC (2006)
Xiaoyue Wang, Mingqi Chen, Luca Macchiarulo, Olga Boric-Lubecke
Fully-Integrated Heart Rate Variability Monitoring System with an Efficient Memory. EMBC (2006)
Mario R. Casu, Luca Macchiarulo
Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Mario R. Casu, Luca Macchiarulo
A New System Design Methodology for Wire Pipelined SoC. DATE (2005)
Mario R. Casu, Luca Macchiarulo
Throughput-driven floorplanning with wire pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Mario R. Casu, Luca Macchiarulo
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD (2005)
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53 (9) (2004)
Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI (2004)
Mario R. Casu, Luca Macchiarulo
Floorplanning for throughput. ISPD (2004)
Mario R. Casu, Luca Macchiarulo
Issues in Implementing Latency Insensitive Protocols. DATE (2004)
Mario R. Casu, Luca Macchiarulo
On-Chip Transparent Wire Pipelining. ICCD (2004)
Mario R. Casu, Luca Macchiarulo
A new approach to latency insensitive design. DAC (2004)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
New techniques for efficiently assessing reliability of SOCs. Microelectron. J. 34 (1) (2003)
Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
PITIA: an FPGA for throughput-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Luca Macchiarulo, Enrico Macii, Massimo Poncino
Wire Placement for Crosstalk Energy Minimization in Address Buses. DATE (2002)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electron. Test. 18 (3) (2002)
Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
Layout-driven memory synthesis for embedded systems-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 10 (2) (2002)
Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
Enhanced clustered voltage scaling for low power. ACM Great Lakes Symposium on VLSI (2002)
Pierluigi Civera, Luca Macchiarulo, Massimo Violante
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT (2002)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium (2001)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL (2001)
Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. DAC (2001)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW (2001)
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT (2001)
Luca Macchiarulo, Enrico Macii, Massimo Poncino
Low-energy for deep-submicron address buses. ISLPED (2001)
Luca Macchiarulo, Luca Benini, Enrico Macii
On-the-fly layout generation for PTL macrocells. DATE (2001)
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
Wave Steered FSMs. DATE (2000)
Elena Dubrova, Luca Macchiarulo
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. IEEE Trans. Computers 49 (11) (2000)
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
A novel high throughput reconfigurable FPGA architecture. FPGA (2000)
Luca Macchiarulo, Malgorzata Marek-Sadowska
Wave-steering one-hot encoded FSMs. DAC (2000)
Luca Macchiarulo, Pierluigi Civera
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. VLSI Design (1999)
Luca Macchiarulo, Pierluigi Civera
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. ISMVL (1998)
Y. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti
Artificial Neural Networks for Motion Emulation in Virtual Environments. CAPTECH (1998)