Davide Pandini

Publication Activity (10 Years)

Years Active: 1993-2013
Publications (10 Years): 0

Top Topics

Hardware And Software

Design Methodology

Top Venues

Publications

Marco Cazzaniga, Patrice Joubert Doriol, Aurora Sanna, Emmanuel Blanc, Valentino Liberali, Davide Pandini
Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers. EMC Compo (2013)
Andrea Manuzzato, Fabio Campi, Valentino Liberali, Davide Pandini
Design methodology for low-power embedded microprocessors. PATMOS (2013)
Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini
Exploiting body biasing for leakage reduction: A case study. ISVLSI (2013)
Marco Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, Valentino Liberali, Davide Pandini
Evaluating the impact of substrate on power integrity in industrial microcontrollers. PATMOS (2013)
Christian Pilato, Fabrizio Ferrandi, Davide Pandini
Evaluating Static CMOS Complex Cells in Technology Mapping. ARCS Workshops (2011)
Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops (2011)
Christian Pilato, Fabrizio Ferrandi, Davide Pandini
A design methodology for the automatic sizing of standard-cell libraries. ACM Great Lakes Symposium on VLSI (2011)
Nikolaos Andrikos, Luciano Lavagno, Fabio Campi, Davide Pandini
Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization. J. Low Power Electron. 6 (4) (2010)
Christian Pilato, Fabrizio Ferrandi, Davide Pandini
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells. ISVLSI (2010)
Cristiano Forzan, Davide Pandini
Statistical static timing analysis: A survey. Integr. 42 (3) (2009)
Davide Pandini
Variability in Advanced Nanometer Technologies: Challenges and Solutions. PATMOS (2009)
Davide Pandini, Guido A. Repetto, Vincenzo Sinisi
Clock-tree synthesis for low-EMI design. J. Embed. Comput. 3 (3) (2009)
Patrice Joubert Doriol, Yamarita Villavicencio, Cristiano Forzan, Mario Rotigni, Giovanni Graziosi, Davide Pandini
EMC-aware design on a microcontroller for automotive applications. DATE (2009)
Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello
Robust Design-for-Productization Practices for High Quality Automotive Products. ITC (2008)
Cristiano Forzan, Davide Pandini
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis CoRR (2007)
Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi
Computing and design for software and silicon manufacturing. VLSI-SoC (2007)
Davide Pandini, Guido A. Repetto, Vincenzo Sinisi
Clock Distribution Techniques for Low-EMI Design. PATMOS (2007)
Davide Pandini
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. IOLTS (2007)
Davide Pandini
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. PATMOS (2007)
Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou
A Fully-Automated Desynchronization Flow for Synchronous Circuits. DAC (2007)
Cristiano Forzan, Davide Pandini
Why we need statistical static timing analysis. ICCD (2007)
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. ISVLSI (2007)
Luca Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago
An ultra-low energy asynchronous processor for Wireless Sensor Networks. ASYNC (2006)
Cristiano Forzan, Davide Pandini, Mariagrazia Graziano
Power Supply Selective Mapping for Accurate Timing Analysis. J. Low Power Electron. 2 (1) (2006)
Davide Pandini, Guido A. Repetto
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. PATMOS (2006)
Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
Power Supply Selective Mapping for Accurate Timing Analysis. PATMOS (2005)
Cristiano Forzan, Davide Pandini
A complete methodology for an accurate static noise analysis. ACM Great Lakes Symposium on VLSI (2005)
Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow. SoCC (2005)
Cristiano Forzan, Davide Pandini
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. DATE (2005)
Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI (2004)
Davide Pandini, Cristiano Forzan, Livio Baldi
Design Methodologies and Architecture Solutions for High-Performance Interconnects. ICCD (2004)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI (2003)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Understanding and addressing the impact of wiring congestion during technology mapping. ISPD (2002)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Congestion-Aware Logic Synthesis. DATE (2002)
Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro
Crosstalk Aware Static Timing Analysis: A Two Step Approach. ISQED (2000)
Davide Pandini, Primo Scandolara, Carlo Guardiani
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. ASP-DAC (1998)
Bruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani
Nonlinear macromodels of large coupled interconnect networks. CICC (1998)
Enrico Malavasi, Davide Pandini
Optimum CMOS stack generation with analog constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (1) (1995)
Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli
Simultaneous Placement and Module Optimization of Analog IC's. DAC (1994)
Valentino Liberali, Enrico Malavasi, Davide Pandini
Automatic Generation of Transistor Stacks for CMOS Analog Layout. ISCAS (1993)