Christos P. Sotiriou

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 22

Top Topics

Takagi Sugeno Fuzzy

Top Venues

Publications

Christos P. Sotiriou, George Rafael Goudroumanis, Nikolaos Sketopoulos, Christos Georgakidis
Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm. ISQED (2024)
Stavros Simoglou, Iordanis Lilitsis, Nikolaos Blias, Christos P. Sotiriou
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. ISQED (2024)
Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Ilias Golfos, Marko S. Andjelkovic, Christos P. Sotiriou, Milos Krstic
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. DFT (2023)
Felipe A. Kuentzer, Christos Georgakidis, Christos P. Sotiriou, Milos Krstic
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers. SBCCI (2023)
Christos Georgakidis, Stavros Simoglou, Christos P. Sotiriou
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening. DFT (2022)
Nikolaos Chatzivangelis, Dimitris Valiantzas, Christos P. Sotiriou, Iordanis Lilitsis
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. VLSI-SoC (2022)
Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. VLSI-SoC (2022)
Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs. IEEE Access 9 (2021)
Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29 (4) (2021)
Christos Georgakidis, Iordanis Lilitsis, Georgios Stanimeropoulos, Christos P. Sotiriou
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints. DFT (2021)
Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. DFT (2021)
Christos Georgakidis, Christos P. Sotiriou
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL. DFT (2020)
Stavros Simoglou, Christos P. Sotiriou, Dimitris Valiantzas, Nikolaos Sketopoulos
STA for Mixed Cyclic, Acyclic Circuits. ISVLSI (2020)
Christos Georgakidis, Georgios Ioannis Paliaroutis, Nikolaos Sketopoulos, Pelopidas Tsoumanis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic. ISQED (2020)
Stavros Simoglou, Nikolaos Xiromeritis, Christos P. Sotiriou, Nikolaos Sketopoulos
Graph-based STA for asynchronous controllers. Integr. 75 (2020)
Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis
Metal Stack and Partitioning Exploration for Monolithic 3D ICs. ISVLSI (2020)
Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic, Oliver Schrape, Anselm Breitenreiter
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. ISVLSI (2020)
Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias
Timing Errors in STA-based Gate-Level Simulation. ASYNC (2020)
Nikolaos Xiromeritis, Stavros Simoglou, Christos P. Sotiriou, Nikolaos Sketopoulos
Graph-Based STA for Asynchronous Controllers. PATMOS (2019)
Nikolaos Sketopoulos, Christos P. Sotiriou, Vasileios Samaras
Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/A. ACM Great Lakes Symposium on VLSI (2019)
Nikolaos Sketopoulos, Christos P. Sotiriou, Stavros Simoglou
Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies. DATE (2018)
Neela Lohith Penmetsa, Christos P. Sotiriou, Sung Kyu Lim
Low Power Monolithic 3D IC Design of Asynchronous AES Core. ASYNC (2015)
Ron Diamant, Ran Ginosar, Christos P. Sotiriou
Asynchronous sub-threshold ultra-low power processor. PATMOS (2015)
Pavlos M. Mattheakis, Christos P. Sotiriou
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. VLSI Design (2013)
Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel
A polynomial time flow for implementing free-choice Petri-nets. ICCD (2012)
Evriklis Kounalakis, Christos P. Sotiriou
SCPlace: A statistical slack-assignment based constructive placer. ISQED (2011)
Gianluca Bontempi, Benjamin Haibe-Kains, Christine Desmedt, Christos P. Sotiriou, John Quackenbush
Multiple-input multiple-output causal strategies for gene selection. BMC Bioinform. 12 (2011)
Evriklis Kounalakis, Christos P. Sotiriou, Vassilis Zebilis
Statistical Timing-Based Post-Placement Leakage Recovery. ISVLSI (2011)
Qiyuan Li, Aron C. Eklund, Nicolai J. Birkbak, Christine Desmedt, Benjamin Haibe-Kains, Christos P. Sotiriou, W. Fraser Symmans, Lajos Pusztai, Søren Brunak, Andrea L. Richardson, Zoltan Szallasi
Consistent metagenes from cancer expression profiles yield agent specific predictors of chemotherapy response. BMC Bioinform. 12 (2011)
Evriklis Kounalakis, Christos P. Sotiriou
CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits. ASYNC (2011)
Benjamin Haibe-Kains, Christine Desmedt, Christos P. Sotiriou, Gianluca Bontempi
A comparative study of survival models for breast cancer prognostication based on microarray data: does a single gene beat them all? Bioinform. 24 (19) (2008)
Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou
A Fully-Automated Desynchronization Flow for Synchronous Circuits. DAC (2007)
Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
High Rate Data Synchronization in GALS SoCs. IEEE Trans. Very Large Scale Integr. Syst. 14 (10) (2006)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. FPL (2006)
Vassilis Zebilis, Christos P. Sotiriou
Controlling Event Spacing in Self-Timed Rings. ASYNC (2005)
Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
Data Synchronization Issues in GALS SoCs. ASYNC (2004)
Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou
Design-space exploration of the most widely used cryptography algorithms. Microprocess. Microsystems 28 (10) (2004)
Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE (2004)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
From Synchronous to Asynchronous: An Automatic Approach. DATE (2004)
Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
Handshake Protocols for De-Synchronization. ASYNC (2004)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
Coping with The Variability of Combinational Logic Delays. ICCD (2004)
Christos P. Sotiriou, Ioannis Papaefstathiou
Design-space exploration of a cryptography algorithm. ICECS (2003)
Manish Amde, Ivan Blunno, Christos P. Sotiriou
Automating the design of an asynchronous DLX microprocessor. DAC (2003)
Ioannis Papaefstathiou, Christos P. Sotiriou
Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture. WCAE (2002)
Christos P. Sotiriou
Implementing asynchronous circuits using a conventional EDA tool-flow. DAC (2002)