Oliver Schrape

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 34

Top Topics

Error Resilient

Top Venues

Publications

Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic
SET and SEU Hardened Clock Gating Cell. DCIS (2023)
Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic
Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting. IEEE Access 10 (2022)
Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, J. Gutiérrez, Milos Krstic, Eckhard Grass
Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS. EuCNC (2022)
Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, J. Gutiérrez, Milos Krstic, Eckhard Grass, Rolf Kraemer
Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS. VTC Spring (2022)
Marko S. Andjelkovic, Aleksandar Simevski, Junchao Chen, Oliver Schrape, Zoran Stamenkovic, Milos Krstic, Stefan D. Ilic, Goran S. Ristic, Aleksandar Jaksic, Nikola Vasovic, Russell Duane, Alberto J. Palma, Antonio M. Lallena, Miguel A. Carvajal
A design concept for radiation hardened RADFET readout system for space applications. Microprocess. Microsystems 90 (2022)
Marko S. Andjelkovic, Milos Marjanovic, Bojan Drasko, Cristiano Calligaro, Oliver Schrape, Umberto Gatti, Felipe A. Kuentzer, Stefan D. Ilic, Goran S. Ristic, Milos Krstic
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors. J. Circuits Syst. Comput. 31 (18) (2022)
Li Lu, Junchao Chen, Anselm Breitenreiter, Oliver Schrape, Markus Ulbricht, Milos Krstic
Machine Learning Approach for Accelerating Simulation-based Fault Injection. NorCAS (2021)
Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Junchao Chen, Milos Krstic
A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells. DFT (2021)
Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler, Milos Krstic
Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. LASCAS (2021)
Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Steffen Zeidler, Alexey Balashov, Milos Krstic
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (11) (2021)
Anselm Breitenreiter, Oliver Schrape, Marko S. Andjelkovic, Milos Krstic
Reliability Analysis in Less than 200 Lines of Code. LASCAS (2021)
Marko S. Andjelkovic, Junchao Chen, Aleksandar Simevski, Oliver Schrape, Milos Krstic, Rolf Kraemer
Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters. CoRR (2021)
Florian Frankreiter, Anselm Breitenreiter, Oliver Schrape, Milos Krstic
Power- and Area-optimized Neural Network IC-Design for Academic Education. ICECS (2021)
Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic
Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops. DSD (2020)
Steffen Zeidler, Oliver Schrape, Anselm Breitenreiter, Milos Krstic
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. DSD (2020)
Felipe A. Kuentzer, Moisés Herrera, Oliver Schrape, Peter A. Beerel, Milos Krstic
Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures. ASYNC (2020)
Marko S. Andjelkovic, Aleksandar Simevski, Junchao Chen, Oliver Schrape, Zoran Stamenkovic, Milos Krstic, Stefan Ilic, Luka Spahic, Laza Kostic, Goran S. Ristic, Aleksandar Jaksic, Alberto J. Palma, Antonio M. Lallena, Miguel Angel Carvaja
Design of Radiation Hardened RADFET Readout System for Space Applications. DSD (2020)
Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic, Rolf Kraemer
Characterization of Single Event Transient Effects in Standard Delay Cells. ICECS (2020)
Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic, Oliver Schrape, Anselm Breitenreiter
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. ISVLSI (2020)
Aleksandar Simevski, Oliver Schrape, Carlos Benito, Milos Krstic, Marko S. Andjelkovic
PISA: Power-robust Multiprocessor Design for Space Applications. IOLTS (2020)
Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler, Milos Krstic
Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. DSD (2019)
Anselm Breitenreiter, Stefan Weidling, Oliver Schrape, Steffen Zeidler, Pedro Reviriego, Milos Krstic
Selective Fault Tolerance by Counting Gates with Controlling Value. IOLTS (2019)
Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. DDECS (2018)
Marko S. Andjelkovic, Milan Babic, Yuanqing Li, Oliver Schrape, Milos Krstic, Rolf Kraemer
Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates. ICECS (2018)
Oliver Schrape, Anselm Breitenreiter, Marko S. Andjelkovic, Milos Krstic
D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop. DSD (2018)
Oliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito, Milos Krstic
Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design. NORCAS (2018)
P. Ostrovsky, Oliver Schrape, Klaus Tittelbach-Helmrich, Frank Herzel, Gunter Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, Dietmar Kissinger
A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer. NORCAS (2018)
Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi
Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment. ACM Great Lakes Symposium on VLSI (2018)
Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. DCIS (2018)
Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. DDECS (2017)
P. Ostrovsky, Klaus Tittelbach-Helmrich, Frank Herzel, Oliver Schrape, Gunter Fischer, Dietmar Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh
A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology. NORCAS (2017)
Oliver Schrape, Arkadiusz Koczor, Piotr Penkala, Vladimir Petrovic, Milos Krstic
Implementation of DBFN processor for Synthetic Aperture Radar application. DDECS (2016)
Xin Fan, Mikkel B. Stegmann, Oliver Schrape, Steffen Zeidler, Isac G. Jensen, Jannich Thorsen, Tobias Bjerregaard, Milos Krstic
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
An Early Stage Design Flow for Switching Noise Attenuation. J. Circuits Syst. Comput. 25 (3) (2016)
Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
A Design Preconditioning Flow for Low-Noise Circuits. DDECS (2015)
Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
Low-power design methodology for CML and ECL circuits. PATMOS (2014)
Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic, Eckhard Grass
GALS Design for Spectral Peak Attenuation of Switching Current. ASYNC (2013)
Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface. ICECS (2013)
Goran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich
TNODE: A low power sensor node processor for secure wireless networks. ISSoC (2013)
Oliver Schrape, Frank Vater
Embedded low power clock generator for sensor nodes. NORCHIP (2012)
Goran Panic, Thomas Basmer, Oliver Schrape, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich
Sensor node processor for security applications. ICECS (2011)
Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. PATMOS (2010)
Frank Winkler, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold
HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. MBMV (2009)