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Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.

Yuanqing LiAnselm BreitenreiterMarko S. AndjelkovicOliver SchrapeMilos Krstic
Published in: DDECS (2018)
Keyphrases
  • duty cycle
  • flip flops
  • real time
  • multiple input
  • power dissipation
  • power consumption
  • master slave
  • computer vision
  • data structure
  • cmos technology
  • clock frequency