Low-power design methodology for CML and ECL circuits.
Oliver SchrapeMarkus AppelFrank WinklerMilos KrsticPublished in: PATMOS (2014)
Keyphrases
- design methodology
- low power
- high speed
- power dissipation
- logic circuits
- cmos technology
- delay insensitive
- power reduction
- vlsi circuits
- power consumption
- low cost
- mixed signal
- chip design
- single chip
- physical design
- design process
- fuzzy neural network
- gate array
- digital signal processing
- low power consumption
- formal specification
- case study
- multi channel
- circuit design
- image sensor
- object oriented
- neural network