Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS.
Lukasz LopacinskiAlireza HasaniGoran PanicNebojsa MaleticOliver SchrapeJ. GutiérrezMilos KrsticEckhard GrassRolf KraemerPublished in: VTC Spring (2022)
Keyphrases
- high speed
- low density parity check
- low power
- ldpc codes
- distributed source coding
- cmos technology
- decoding algorithm
- distributed video coding
- turbo codes
- low complexity
- error correction
- compressive sensing
- channel coding
- nm technology
- real time
- frame rate
- error concealment
- error resilience
- rate allocation
- focal plane
- message passing
- error resilient
- video codec
- motion estimation