Dimitrios Garyfallou

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 17

Top Topics

Accurate Estimation

Low Rank Matrix Recovery

Parallel Architectures

Lower Error Rates

Top Venues

Publications

Dimitrios Garyfallou, Athanasios Stefanou, Christos Giamouzis, Moschos Antoniadis, Georgios Chararas, Konstantinos Chatzis, Dimitris Samaras, Rafaela Themeli, Anastasios Michailidis, Vasiliki Gogolou, Nikos Zachos, Nestor E. Evmorfopoulos, Thomas Noulis, Vasilis F. Pavlidis, Alkiviadis Hatzopoulos, Elpida Chatzineofytou, Yiannis Moisiadis
MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits. CoRR (2024)
Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential. SMACD (2023)
Christos Giamouzis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor E. Evmorfopoulos
Reduction of large-scale RLCk models via low-rank balanced truncation. CoRR (2023)
Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis
Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis. DFT (2023)
Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George Stamoulis
A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential. ASP-DAC (2023)
Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance. ACM Great Lakes Symposium on VLSI (2022)
Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis
A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential. CoRR (2022)
Pavlos Stoikos, Dimitrios Garyfallou, George Floros, Nestor E. Evmorfopoulos, George I. Stamoulis
The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models. CoRR (2022)
Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou, George Floros, Nestor E. Evmorfopoulos, George I. Stamoulis
Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models. ASP-DAC (2021)
Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou, George Floros, Nestor E. Evmorfopoulos, George I. Stamoulis
Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models. CoRR (2020)
Dimitrios Garyfallou, Ioannis Tsiokanos, Nestor E. Evmorfopoulos, Georgios I. Stamoulis, Georgios Karakonstantis
Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation. ISQED (2020)
Dimitrios Garyfallou, Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects. SMACD (2019)
Charalampos Antoniadis, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
EVT-based worst case delay estimation under process variation. DATE (2018)
Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s. SMACD (2018)
Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis
Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures. MOCAST (2018)
Antonios N. Dadaliaris, Panagiotis Oikonomou, Maria G. Koziri, Evangelia Nerantzaki, Yannis Hatzaras, Dimitrios Garyfallou, Thanasis Loukopoulos, Georgios I. Stamoulis
Heuristics to Augment the Performance of Tetris Legalization: Making a Fast but Inferior Method Competitive. J. Low Power Electron. 13 (2) (2017)