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A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects.
Dimitrios Garyfallou
Charalampos Antoniadis
Nestor E. Evmorfopoulos
Georgios I. Stamoulis
Published in:
SMACD (2019)
Keyphrases
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input output
vlsi design
pattern recognition
high dimensional
computationally efficient
power dissipation
databases
signal processing
sparse representation
high precision
neural network
information retrieval
learning algorithm
case study
low cost