Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Christos GeorgakidisDimitris ValiantzasStavros SimoglouIordanis LilitsisNikolaos ChatzivangelisIlias GolfosMarko S. AndjelkovicChristos P. SotiriouMilos KrsticPublished in: DFT (2023)