Vassilis Papaefstathiou

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 33

Top Topics

Parallel Architectures

Error Correcting Codes

Systematic Evaluation

Cache Management

Top Venues

ACM Trans. Archit. Code Optim.

Publications

Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos
Low-latency Communication in RISC-V Clusters. HPC Asia (2024)
Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, Jesús Labarta
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study. CoRR (2023)
Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF (2023)
Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani
Short reasons for long vectors in HPC CPUs: a study based on RISC-V. CoRR (2023)
Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani
Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V. SC Workshops (2023)
Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta
Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study. ISC Workshops (2023)
Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Asiminakis, Vassilis Flouris, Nikolaos D. Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Polydoros Petrakis, Nikolaos Dimou, Michalis Gianioudis, Georgios Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Georgios Ailamakis, Astrinos Damianakis, Michael Ligerakis, Ioannis Makris, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, Iakovos Mavroidis
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. CoRR (2023)
Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis
Optimized Page Fault Handling During RDMA. IEEE Trans. Parallel Distributed Syst. 33 (10) (2022)
Ahsen Ejaz, Vassilis Papaefstathiou, Ioannis Sourdis
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers. IEEE/ACM Trans. Netw. 29 (1) (2021)
Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS (2021)
Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Giannioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis
PART: Pinning Avoidance in RDMA Technologies. NOCS (2020)
George Christou, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, Sotiris Ioannidis
On Architectural Support for Instruction Set Randomization. ACM Trans. Archit. Code Optim. 17 (4) (2020)
David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Giuliano Taffoni, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti
Performance and energy footprint assessment of FPGAs and GPUs on HPC systems using Astrophysics application. CoRR (2020)
David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, Giuliano Taffoni
Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application. Comput. 8 (2) (2020)
Miquel Pericàs, Oscar Palomar, Vassilis Papaefstathiou, Mahmoud Eljammaly
Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020). CoRR (2020)
Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems. HPCA (2020)
Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
LLC-Guided Data Migration in Hybrid Memory Systems. IPDPS (2019)
Manolis Ploumidis, Nikolaos D. Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou, Manolis Katevenis
Software and Hardware Co-design for Low-Power HPC Platforms. ISC Workshops (2019)
Fabien Chaix, Georgios Ailamakis, Theocharis Vavouris, Astrinos Damianakis, Manolis Katevenis, Iakovos Mavroidis, Aggelos Ioannou, Nikolaos Kossifidis, Nikolaos Dimou, Giorgos Ieronymakis, Manolis Marazakis, Vassilis Papaefstathiou, Vassilis Flouris, Mihailis Ligerakis
Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping. H2RC@SC (2019)
Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti
Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures. PARCO (2019)
Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache. ACM Trans. Archit. Code Optim. 15 (4) (2019)
George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Xiaojun Yang, Dionisios N. Pnevmatikatos, Manolis Katevenis
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Trans. High Perform. Embed. Archit. Compil. 5 (2019)
David Goz, Giorgos Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti
Direct N-body application on low-power and energy-efficient parallel architectures. CoRR (2019)
Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. HPCA (2018)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. 15 (3) (2018)
Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
FusionCache: Using LLC tags for DRAM cache. DATE (2018)
Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16 (2) (2017)
Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Odd-ECC: on-demand DRAM error correcting codes. MEMSYS (2017)
Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis
Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. PATMOS (2017)
Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
RADAR: Runtime-assisted dead region management for last-level caches. HPCA (2016)
Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. DATE (2016)
Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. MEMSYS (2016)
Antonis Psathakis, Vassilis Papaefstathiou, Nikolaos Chrysos, Fabien Chaix, Evangelos Vasilakis, Dionisios N. Pnevmatikatos, Manolis Katevenis
A Systematic Evaluation of Emerging Mesh-like CMP NoCs. ANCS (2015)
Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos
Design trade-offs in energy efficient NoC architectures. NOCS (2014)
Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Iakovos Mavroidis, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos
FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards. J. Syst. Archit. 60 (6) (2014)
Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos
Design space exploration for fair resource-allocated NoC architectures. ICSAMOS (2014)
Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Stamatis G. Kavadias, Manolis Katevenis
NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. J. Syst. Archit. 59 (1) (2013)
Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis
ASIST: architectural support for instruction set randomization. CCS (2013)
Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios S. Nikolopoulos, Dionisios N. Pnevmatikatos
Prefetching and cache management using task lifetimes. ICS (2013)
Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos
Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. FCCM (2012)
Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis
Fine-grain OpenMP runtime support with explicit communication hardware primitives. DATE (2011)
Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. ReConFig (2010)
Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos, Federico Silla, Dimitrios S. Nikolopoulos
Explicit Communication and Synchronization in SARC. IEEE Micro 30 (5) (2010)
George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. ICSAMOS (2009)
Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas
Optimization and bottleneck analysis of network block I/O in commodity storage systems. ICS (2007)
Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis
Prototyping Efficient Interprocessor Communication Mechanisms. ICSAMOS (2007)
Ioannis Papaefstathiou, Vassilis Papaefstathiou
Memory-Efficient 5D Packet Classification At 40 Gbps. INFOCOM (2007)
Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas
Efficient remote block-level I/O over an RDMA-capable NIC. ICS (2006)
Ioannis Papaefstathiou, Vassilis Papaefstathiou
An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks. ICC (2006)
Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas
Experiences from Debugging a PCIX-based RDMA-capable NIC. CLUSTER (2006)
Vassilis Papaefstathiou, Ioannis Papaefstathiou
A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE Designers' Forum (2006)
Vassilis Papaefstathiou, Ioannis Papaefstathiou
A Memory Efficient, 100 Gb/sec MAC Classification Engine. LCN (2005)
Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou
Design-space exploration of the most widely used cryptography algorithms. Microprocess. Microsystems 28 (10) (2004)