Adrià Armejach

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 30

Top Topics

Top Venues

J. Supercomput.

IEEE ACM Trans. Comput. Biol. Bioinform.

Publications

Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó
GenArchBench: A genomics benchmark suite for arm HPC processors. Future Gener. Comput. Syst. 157 (2024)
Francesc Martínez Palau, Martí Torrents, Adrià Armejach, Marc Casas
Exploiting Vector Code Semantics for Efficient Data Cache Prefetching. ICS (2024)
Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard
A Mess of Memory System Benchmarking, Simulation and Application Profiling. CoRR (2024)
Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó
Characterization of a Coherent Hardware Accelerator Framework for SoCs. SAMOS (2023)
Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach
A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. MICRO (2023)
Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó
DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. ISCA (2023)
Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó
SpChar: Characterizing the Sparse Puzzle via Decision Trees. CoRR (2023)
Alexandre de Limas Santana, Adrià Armejach, Marc Casas
Efficient Direct Convolution Using Long SIMD Instructions. PPoPP (2023)
Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó
Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. IEEE ACM Trans. Comput. Biol. Bioinform. 20 (5) (2023)
Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. DATE (2023)
John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
A BF16 FMA is All You Need for DNN Training. ARITH (2022)
John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ISPASS (2022)
John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ECML/PKDD (5) (2022)
John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
A BF16 FMA is All You Need for DNN Training. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó
Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. IEEE ACM Trans. Comput. Biol. Bioinform. 19 (1) (2022)
Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. DATE (2021)
Guillem López-Paradís, Adrià Armejach, Miquel Moretó
gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator. ICPP (2021)
Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó
On the use of many-core Marvell ThunderX2 processor for HPC workloads. J. Supercomput. 77 (4) (2021)
Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS (2021)
John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. ICMLA (2021)
Adrián Barredo, Adrià Armejach, Jonathan C. Beard, Miquel Moretó
PLANAR: a programmable accelerator for near-memory data rearrangement. ICS (2021)
John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, Marc Casas
Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. ICMLA (2020)
Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian
The gem5 Simulator: Version 20.0+. CoRR (2020)
Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76 (3) (2020)
Adrià Armejach, Marc Casas, Miquel Moretó
Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. 75 (9) (2019)
Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas
Design Space Exploration of Next-Generation HPC Machines. IPDPS (2019)
Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
Stencil codes on a vector length agnostic architecture. PACT (2018)
Naveed Ul Mustafa, Adrià Armejach, Özcan Özturk, Adrián Cristal, Osman S. Unsal
Implications of non-volatile memory as primary storage for database management systems. SAMOS (2016)
Oriol Arcas-Abella, Adrià Armejach, Timothy Hayes, Gorker Alp Malazgirt, Oscar Palomar, Behzad Salami, Nehir Sönmez
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. Comput. Sci. Eng. 18 (1) (2016)
Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó
MUSA: a multi-level simulation approach for next-generation HPC machines. SC (2016)
Adrià Armejach, Adrián Cristal, Osman S. Unsal
Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches. SBAC-PAD (2015)
Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song, John Mawer, Adrián Cristal, Mikel Luján
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. FPL (2014)
Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC (2013)
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
Circuit design of a dual-versioning L1 data cache. Integr. 45 (3) (2012)
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero
Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP (2012)
Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström
Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT (2012)
Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT (2011)
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI (2011)
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero
EazyHTM: eager-lazy hardware transactional memory. MICRO (2009)