Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
Azam SeyediAdrià ArmejachAdrián CristalOsman S. UnsalIbrahim HurMateo ValeroPublished in: ACM Great Lakes Symposium on VLSI (2011)
Keyphrases
- data sets
- data analysis
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- database
- input data
- circuit design
- high dimensional data
- prior knowledge
- image data
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- statistical analysis
- high quality
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- main memory
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- end users
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- knowledge discovery
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- high dimensional
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