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Balaji Venu
ORCID
Publication Activity (10 Years)
Years Active: 2011-2023
Publications (10 Years): 8
Top Topics
Autonomous Vehicles
Pc Cluster
Regulatory Requirements
Buffer Overflow
Top Venues
CASES
MICRO
SAMOS
IEEE Des. Test
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Publications
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Guillem López-Paradís
,
Balaji Venu
,
Adrià Armejach
,
Miquel Moretó
Characterization of a Coherent Hardware Accelerator Framework for SoCs.
SAMOS
(2023)
Matteo Andreozzi
,
Giacomo Gabrielli
,
Balaji Venu
,
Giacomo Travaglini
Industrial Challenge 2022: A High-Performance Real-Time Case Study on Arm.
ECRTS
(2022)
Xabier Iturbe
,
Balaji Venu
,
Emre Ozer
,
Jean-Luc Poupat
,
Gregoire Gimenez
,
Hans-Ulrich Zurek
The Arm Triple Core Lock-Step (TCLS) Processor.
ACM Trans. Comput. Syst.
36 (3) (2019)
Emre Ozer
,
Balaji Venu
,
Xabier Iturbe
,
Shidhartha Das
,
Spyros Lyberis
,
John Biggs
,
Peter Harrod
,
John Penton
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems.
MICRO
(2018)
Xabier Iturbe
,
Balaji Venu
,
Juergen Jagst
,
Emre Ozer
,
Peter Harrod
,
Chris Turner
,
John Penton
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture.
IEEE Des. Test
35 (3) (2018)
Xabier Iturbe
,
Balaji Venu
,
John Penton
,
Emre Ozer
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress.
CASES
(2017)
Xabier Iturbe
,
Balaji Venu
,
Emre Ozer
,
Shidhartha Das
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications.
DSN Workshops
(2016)
Xabier Iturbe
,
Balaji Venu
,
Emre Ozer
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU.
DFT
(2016)
Balaji Venu
,
Ashwani Singh
Formal verification methodology considerations for network on chips.
ICACCI
(2012)
Balaji Venu
Multi-core processors - An overview
CoRR
(2011)