Shidhartha Das

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 45

Top Topics

Software And Hardware Implementations

Special Session

Error Correction

Top Venues

IEEE J. Solid State Circuits

Publications

Kanishkan Vadivel, Fernando García-Redondo, Ali BanaGozar, Henk Corporaal, Shidhartha Das
SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator. DCIS (2022)
Fernando García-Redondo, Ali BanaGozar, Kanishkan Vadivel, Henk Corporaal, Shidhartha Das
SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components. DCIS (2022)
Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung
System technology co-optimization and design challenges for 3D IC. CICC (2022)
Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 57 (1) (2022)
Chuteng Zhou, Fernando García-Redondo, Julian Büchel, Irem Boybat, Xavier Timoneda Comas, S. R. Nandakumar, Shidhartha Das, Abu Sebastian, Manuel Le Gallo, Paul N. Whatmough
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator. IEEE Micro 42 (6) (2022)
Chuteng Zhou, Fernando García-Redondo, Julian Büchel, Irem Boybat, Xavier Timoneda Comas, S. R. Nandakumar, Shidhartha Das, Abu Sebastian, Manuel Le Gallo, Paul N. Whatmough
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator. CoRR (2021)
George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Greg Favor, Kumar Sankaran, Shidhartha Das
A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs. CoRR (2021)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers 70 (9) (2021)
Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. ISLPED (2021)
Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO (2021)
Sanu Mathew, Shidhartha Das, Hugh Mair
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. ISSCC (2021)
Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
Simultaneous Wireless Inter-Tier Data and Power Transfer. VLSI Circuits (2020)
Fernando García-Redondo, Shidhartha Das, Glen Rosendale
Training DNN IoT Applications for Deployment On Analog NVM Crossbars. IJCNN (2020)
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR (2020)
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration. IEEE J. Solid State Circuits 55 (9) (2020)
Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration. ESSCIRC (2019)
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. ISLPED (2019)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS (2019)
Sergey Mileiko, Thanasin Bunnam, Fei Xia, Rishad A. Shafik, Alex Yakovlev, Shidhartha Das
Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding. CoRR (2019)
Matthew Douthwaite, Fernando García-Redondo, Pantelis Georgiou, Shidhartha Das
A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics. BioCAS (2019)
Fernando García-Redondo, Shidhartha Das, Glen Rosendale
Training DNN IoT Applications for Deployment On Analog NVM Crossbars. CoRR (2019)
Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando García-Redondo, Geethan Karunaratne, Abbas Rahimi, Luca Benini
Applications of Computation-In-Memory Architectures based on Memristive Devices. DATE (2019)
Vasileios Tenentes, Shidhartha Das, Daniele Rossi, Bashir M. Al-Hashimi
Run-time Detection and Mitigation of Power-Noise Viruses. IOLTS (2019)
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs. DATE (2019)
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
Design and Optimization of Inductive-Coupling Links for 3-D-ICs. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO (2018)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. 17 (1) (2018)
Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops (2018)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO (2018)
Benjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak
Low-power 3D integration using inductive coupling links for neurotechnology applications. DATE (2018)
Andrea Bevilacqua, Shidhartha Das, Pieter Harpe
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 53 (7) (2018)
Rishad A. Shafik, Alex Yakovlev, Shidhartha Das
Real-Power Computing. IEEE Trans. Computers 67 (10) (2018)
Issa Qiqieh, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Shidhartha Das, Alexandre Yakovlev
Significance-Driven Logic Compression for Energy-Efficient Multiplier Design. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (3) (2018)
Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE (2018)
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
A high-speed design methodology for inductive coupling links in 3D-ICs. DATE (2018)
Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor. IEEE J. Solid State Circuits 52 (6) (2017)
George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das
Harnessing voltage margins for energy efficiency in multicore CPUs. MICRO (2017)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED (2017)
Georgios Karakonstantis, Dimitrios S. Nikolopoulos, Dimitris Gizopoulos, Pedro Trancoso, Yiannakis Sazeides, Christos D. Antonopoulos, Srikumar Venugopal, Shidhartha Das
Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer 50 (12) (2017)
Dave Burke, Dainius Jenkus, Issa Qiqieh, Rishad A. Shafik, Shidhartha Das, Alex Yakovlev
Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper. CODES+ISSS (2017)
Vasileios Tenentes, Charles Leech, Graeme M. Bragg, Geoff V. Merrett, Bashir M. Al-Hashimi, Hussam Amrouch, Jörg Henkel, Shidhartha Das
Hardware and software innovations in energy-efficient system-reliability monitoring. DFT (2017)
Issa Qiqieh, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Shidhartha Das, Alex Yakovlev
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression. SiPS (2017)
Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10 (6) (2016)
Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. DSN Workshops (2016)
Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster. ISSCC (2015)
Shidhartha Das, Paul N. Whatmough, David M. Bull
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS. ISLPED (2015)
Paul N. Whatmough, Shidhartha Das, David M. Bull
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation. ISLPED (2015)
Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull
A 0.6V all-digital body-coupled wakeup transceiver for IoT applications. VLSIC (2015)
Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Paul N. Whatmough, Shidhartha Das, David M. Bull
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. IEEE J. Solid State Circuits 49 (1) (2014)
Paul N. Whatmough, Shidhartha Das, David M. Bull
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS. ISSCC (2013)
Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. CICC (2013)
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
Selective time borrowing for DSP pipelines with hybrid voltage control loop. ASP-DAC (2012)
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". IEEE J. Solid State Circuits 46 (3) (2011)
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
Error-resilient low-power DSP via path-delay shaping. DAC (2011)
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. IEEE J. Solid State Circuits 46 (1) (2011)
Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw
A robust FIR filter with in situ error detection. ISCAS (2010)
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC (2010)
Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken
Addressing design margins through error-tolerant circuits. DAC (2009)
Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. Solid State Circuits 44 (1) (2009)
Shidhartha Das, David T. Blaauw
Adaptive Design for Nanometer Technology. ISCAS (2009)
David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. ISSCC (2008)
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull
DVFS in loop accelerators using BLADES. DAC (2008)
Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circuits 41 (4) (2006)
Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
Circuit-aware architectural simulation. DAC (2004)
Dan Ernst, Shidhartha Das, Seokwoo Lee, David T. Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24 (6) (2004)
Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED (2004)
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO (2003)
Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
Optimal Inductance for On-chip RLC Interconnections. ICCD (2003)