Yiannakis Sazeides

Publication Activity (10 Years)

Years Active: 1996-2022
Publications (10 Years): 33

Top Topics

Human Relevance Judgments

Hamming Distance

Error Detection

Document Search

Top Venues

Publications

Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. MICRO (2022)
Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. MICRO (2022)
Panagiota Nikolaou, Yiannakis Sazeides, Alejandro Lampropulos, Denis Guilhot, Andrea Bartoli, George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study. IEEE Trans. Sustain. Comput. 7 (2) (2022)
Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. DFT (2022)
Georgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet, Yiannakis Sazeides, Jawad Haj-Yahya
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. CoRR (2022)
Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. CoRR (2022)
Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. CoRR (2022)
Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Ramon Canal
A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Georgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet, Yiannakis Sazeides, Jawad Haj-Yahya
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. MICRO (2022)
Ramon Canal, Yiannakis Sazeides, Arkady Bramnik
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. DATE (2021)
Alex Gendler, Ernest Knoll, Yiannakis Sazeides
I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling. IEEE Micro 41 (5) (2021)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers 70 (9) (2021)
Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). DFT (2020)
Georgia Antoniou, Zacharias Hadjilambrou, Yiannakis Sazeides
Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application. ISPASS (2020)
Panagiota Nikolaou, Yiannakis Sazeides
Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters. ISPASS (2020)
Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. DATE (2019)
Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS (2019)
Zacharias Hadjilambrou, Marios Kleanthous, Georgia Antoniou, Antoni Portero, Yiannakis Sazeides
Comprehensive Characterization of an Open Source Document Search Engine. ACM Trans. Archit. Code Optim. 16 (2) (2019)
Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris
Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH (2018)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. 17 (1) (2018)
Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops (2018)
Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO (2018)
Alex Gendler, Arkady Bramnik, Ariel Szapiro, Yiannakis Sazeides
Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag. HPCA (2018)
Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE (2018)
Arkady Bramnik, Yiannakis Sazeides
To Detect or to Correct? IOLTS (2018)
Nikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panayiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrík, Martin Golasowski, Jiri Sevcík, Vít Vondrák, Francky Catthoor, William Fornaciari, Dimitrios Soudris
HARPA: Tackling physically induced performance variability. DATE (2017)
Georgios Karakonstantis, Dimitrios S. Nikolopoulos, Dimitris Gizopoulos, Pedro Trancoso, Yiannakis Sazeides, Christos D. Antonopoulos, Srikumar Venugopal, Shidhartha Das
Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer 50 (12) (2017)
Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavrík, Vít Vondrák
A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application. CoRR (2017)
Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. 104 (2017)
Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. 13 (2) (2016)
Damien Hardy, Isabelle Puaut, Yiannakis Sazeides
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. DATE (2016)
Dimitrios Rodopoulos, Philippe Roussel, Francky Catthoor, Yiannakis Sazeides, Dimitrios Soudris
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point. ERMAVSS@DATE (2016)
Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos, Panagiota Nikolaou, Zacharias Hadjilambrou
Toward Multi-Layer Holistic Evaluation of System Designs. IEEE Comput. Archit. Lett. 15 (1) (2016)
Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Marios Kleanthous
Modeling the implications of DRAM failures and protection techniques on datacenter TCO. MICRO (2015)
Dimitrios Rodopoulos, Simone Corbetta, Giuseppe Massari, Simone Libutti, Francky Catthoor, Yiannakis Sazeides, Chrysostomos Nicopoulos, Antoni Portero, Etienne Cappe, Radim Vavrík, Vít Vondrák, Dimitrios Soudris, Federico Sassi, Agnes Fritsch, William Fornaciari
HARPA: Solutions for dependable performance under physically induced performance variability. SAMOS (2015)
Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji
Memory array protection: check on read or check on write? DATE (2013)
Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón
Modeling the impact of permanent faults in caches. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Damien Hardy, Marios Kleanthous, Isidoros Sideris, Ali G. Saidi, Emre Özer, Yiannakis Sazeides
An analytical framework for estimating TCO and exploring data center design space. ISPASS (2013)
Yiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. MICRO (2013)
Boris Grot, Damien Hardy, Pejman Lotfi-Kamran, Babak Falsafi, Chrysostomos Nicopoulos, Yiannakis Sazeides
Optimizing Data-Center TCO with Scale-Out Processors. IEEE Micro 32 (5) (2012)
Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures. MICRO (2012)
Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. MICRO (2012)
Dragomir Milojevic, Sachin Idgunji, Djordje Jevdjic, Emre Özer, Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou, Chrysostomos Nicopoulos, Damien Hardy, Babak Falsafi, Yiannakis Sazeides
Thermal characterization of cloud workloads on a power-efficient server-on-chip. ICCD (2012)
Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. ISLPED (2011)
Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous
Improving Branch Prediction by Considering Affectors and Affectees Correlations. Trans. High Perform. Embed. Archit. Compil. 3 (2011)
Marios Kleanthous, Yiannakis Sazeides
CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, José M. García
An analytical model for the calculation of the Expected Miss Ratio in faulty caches. IOLTS (2011)
Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
Performance-effective operation below Vcc-min. ISPASS (2010)
Pierre Michaud, Yiannakis Sazeides, André Seznec
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers (2010)
Marios Kleanthous, Yiannakis Sazeides, Marios D. Dikaiakos
Extrinsic and Intrinsic Text Cloning. ISCA Workshops (2010)
Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous
The Significance of Affectors and Affectees Correlations for Branch Prediction. HiPEAC (2008)
Marios Kleanthous, Yiannakis Sazeides
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. DATE (2008)
Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. 4 (2) (2007)
Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News 33 (4) (2005)
Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou
The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. IEEE Comput. Archit. Lett. 4 (1) (2005)
Yiannakis Sazeides
Instruction-Isomorphism in Program Execution. J. Instr. Level Parallelism 5 (2003)
Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen
Selecting long atomic traces for high coverage. ICS (2003)
André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA (2002)
Yiannakis Sazeides
Modeling Value Speculation. HPCA (2002)
Yiannakis Sazeides, Toni Juan
How to compare the performance of two SMT microarchitectures. ISPASS (2001)
Yiannakis Sazeides, James E. Smith
Limits of Data Value Predictability. Int. J. Parallel Program. 27 (4) (1999)
Yiannakis Sazeides, James E. Smith
Modeling Program Predictability. ISCA (1998)
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
Trace Processors. MICRO (1997)
Yiannakis Sazeides, James E. Smith
The Predictability of Data Values. MICRO (1997)
Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith
The Performance Potential of Data Dependence Speculation & Collapsing. MICRO (1996)