Giorgos Dimitrakopoulos

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 61

Top Topics

Network Traffic

Error Correction

Lagrangian Relaxation

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos
Error Checking for Sparse Systolic Tensor Arrays. AICAS (2024)
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. CoRR (2024)
Vasileios Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. DATE (2024)
Christodoulos Peltekis, Kosmas Alexandridi, Giorgos Dimitrakopoulos
Reusing Softmax Hardware Unit for GELU Computation in Transformers. CoRR (2024)
Dionysios Filippas, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios Ch. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators. IEEE Access 12 (2024)
Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos
Reusing Softmax Hardware Unit for GELU Computation in Transformers. AICAS (2024)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos
Error Checking for Sparse Systolic Tensor Arrays. CoRR (2024)
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. IEEE Comput. Archit. Lett. 23 (1) (2024)
Giorgos Dimitrakopoulos, E. Kallitsounakis, Z. Takakis, A. Stefanidis, Chrysostomos Nicopoulos
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification. MOCAST (2023)
Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. AICAS (2023)
Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos
Task-Based Parallel Programming for Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Streaming Dilated Convolution Engine. IEEE Trans. Very Large Scale Integr. Syst. 31 (3) (2023)
Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. CoRR (2023)
Apostolos Stefanidis, Ioanna Zoumpoulidou, Dionysios Filippas, Giorgos Dimitrakopoulos, Georgios Ch. Sirakoulis
Synthesis of Approximate Parallel-Prefix Adders. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. CoRR (2023)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos
The Case for Asymmetric Systolic Array Floorplanning. CoRR (2023)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Exploiting data encoding and reordering for low-power streaming in systolic arrays. Microprocess. Microsystems 102 (2023)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. MOCAST (2023)
V. Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. CoRR (2023)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. DATE (2023)
Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride. ISVLSI (2022)
Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. MICRO (2022)
Giorgos Dimitrakopoulos, Anastasios Psarras, Chrysostomos Nicopoulos
Virtual-Channel Flow Control Across Mesochronous Clock Domains. MOCAST (2022)
Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks. ASAP (2022)
Dionysios Filippas, Nikolaos Margomenos, Nikolaos Mitianoudis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Low-Cost Online Convolution Checksum Checker. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. CoRR (2022)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. ARITH (2021)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Dimitrios Mangiras, Giorgos Dimitrakopoulos
Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment. MOCAST (2021)
Dimitris Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Giorgos Dimitrakopoulos
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching. Integr. 77 (2021)
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). DFT (2020)
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis
Memristive Learning Cellular Automata: Theory and Applications. MOCAST (2020)
Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. ISPD (2020)
Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos
RISC-V2: A Scalable RISC-V Vector Processor. ISCAS (2020)
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case. CoRR (2020)
Dimitrios Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos
SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers. ISCAS (2020)
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis
Memristive Learning Cellular Automata: Theory and Applications. CoRR (2020)
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. ISPD (2020)
Dimitrios Konstantinou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
The Mesochronous Dual-Clock FIFO Buffer. IEEE Trans. Very Large Scale Integr. Syst. 28 (1) (2020)
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. ISCAS (2020)
Dimitrios Mangiras, Apostolos Stefanidis, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. DATE (2019)
Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Automatic Generation of Peak-Power Traffic for Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (1) (2019)
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Multi-Armed Bandits for Autonomous Timing-driven Design Optimization. PATMOS (2019)
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (8) (2019)
Zacharias Takakis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage. IVSW (2019)
Dimitris Konstantinou, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
Low-power dual-edge-triggered synchronous latency-insensitive systems. MOCAST (2018)
Karyofyllis Patsidis, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. Microprocess. Microsystems 61 (2018)
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC (2017)
Anastasios Psarras, Michalis Paschou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
A Dual-Clock Multiple-Queue Shared Buffer. IEEE Trans. Computers 66 (10) (2017)
Emmanuel Karampasis, Nick P. Papanikolaou, Dionisis Voglitsis, Michael Loupis, Anastasios Psarras, Alexandros Boubaris, Dimitris Baros, Giorgos Dimitrakopoulos
Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project. IEEE Access 5 (2017)
Monobrata Debnath, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Wei-Ming Lin, Junghee Lee
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling. AISTECS@HiPEAC (2017)
Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Networks-on-Chip With Double-Data-Rate Links. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2017)
Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. 13 (2) (2016)
Michalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
CrossOver: Clock domain crossing under virtual-channel flow control. DATE (2016)
Anastasios Psarras, Junghee Lee, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (5) (2016)
Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip. NOCS (2016)
Anastasios Psarras, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing. IEEE Trans. Computers 65 (10) (2016)
Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
RapidLink: A network-on-chip architecture with double-data-rate links. ICECS (2016)
Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI (2016)
Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Des. Autom. Embed. Syst. 19 (1-2) (2015)
Ioannis Seitanidis, Anastasios Psarras, Kypros Chrysanthou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Anastasios Psarras, I. Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation. DATE (2015)
Alexandros Panteloukas, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Timing-resilient Network-on-Chip architectures. IOLTS (2015)
I. Seitanidis, Anastasios Psarras, Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture. NOCS (2014)
I. Seitanidis, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
ElastiStore: An elastic buffer architecture for Network-on-Chip routers. DATE (2014)
Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag
Editorial. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella
Hardware primitives for the synthesis of multithreaded elastic systems. DATE (2014)
Giorgos Dimitrakopoulos, Emmanouil Kalligeros, Costas Galanopoulos
Merged Switch Allocation and Traversal in Network-on-Chip Switches. IEEE Trans. Computers 62 (10) (2013)
Giorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros
Switch folding: network-on-chip routers with time-multiplexed output ports. DATE (2013)
Haridimos T. Vergos, Giorgos Dimitrakopoulos
On Modulo 2^n+1 Adder Design. IEEE Trans. Computers 61 (2) (2012)
Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Giorgos Dimitrakopoulos, Emmanouil Kalligeros
Low-cost fault-tolerant switch allocator for network-on-chip routers. INA-OCMC@HiPEAC (2012)
Giorgos Dimitrakopoulos, Emmanouil Kalligeros
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches. DATE (2012)
Antoni Roca, José Flich, Giorgos Dimitrakopoulos
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL (2012)
Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks. FPL (2011)
Giorgos Dimitrakopoulos, Kostas Galanopoulos
Switch allocator for bufferless network-on-chip routers. INA-OCMC@HiPEAC (2011)
Nikos Chrysos, Giorgos Dimitrakopoulos
Practical High-Throughput Crossbar Scheduling. IEEE Micro 29 (4) (2009)
Yiouli Kritikou, Giorgos Dimitrakopoulos, E. Dimitrellou, Panagiotis Demestichas
A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric. Telematics Informatics 26 (4) (2009)
Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos
Fast arbiters for on-chip network switches. ICCD (2008)
Nikos Chrysos, Giorgos Dimitrakopoulos
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. Hot Interconnects (2008)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
Sorter Based Permutation Units for Media-Enhanced Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
Fast bit permutation unit for media enhanced microprocessors. ISCAS (2006)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
An Energy-Delay Efficient Subword Permutation Unit. ASAP (2006)
Giorgos Dimitrakopoulos, Dimitris Nikolos
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. PATMOS (2005)
Giorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
New architectures for modulo 2N - 1 adders. ICECS (2005)
Giorgos Dimitrakopoulos, Dimitris Nikolos
High-Speed Parallel-Prefix VLSI Ling Adders. IEEE Trans. Computers 54 (2) (2005)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54 (4) (2005)
Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS (2004)
Giorgos Dimitrakopoulos, Vassilis Paliouras
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2004)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
+1 tree multipliers for diminished-1 operands. ICECS (2003)
Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
- 1 adders. ISCAS (5) (2003)
Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW (2002)