Kleanthis Papachatzopoulos

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 11

Top Topics

Multiple Valued

Top Venues

IEEE Trans. Emerg. Top. Comput.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Kleanthis Papachatzopoulos, Vassilis Paliouras
Path-Based Delay Variation Models for Parallel-Prefix Adders. IEEE Trans. Emerg. Top. Comput. 11 (3) (2023)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. IEEE Trans. Emerg. Top. Comput. 11 (4) (2023)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. ISCAS (2022)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. ARITH (2021)
Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
A Novel Stochastic Polar Architecture for All-Digital Transmission. ISCAS (2021)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Kleanthis Papachatzopoulos, Chris Andriakopoulos, Vassilis Paliouras
Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. ISCAS (2020)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. ARITH (2020)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras
Dynamic delay variation behaviour of RNS multiply-add architectures. ISCAS (2016)