Vassilis Paliouras

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 61

Top Venues

Publications

Francesco Regazzoni, Gergely Ács, Albert Zoltan Aszalos, Christos Avgerinos, Nikolaos Bakalos, Josep Lluis Berral, Joppe W. Bos, Marco Brohet, Andrés G. Castillo Sanz, Gareth T. Davies, Stefanos Florescu, Pierre-Elisée Flory, Alberto Gutierrez-Torre, Evangelos Haleplidis, Alice Héliou, Sotirios Ioannidis, Alexander Islam El-Kady, Katarzyna Kapusta, Konstantina Karagianni, Pieter Kruizinga, Kyrian Maat, Zoltán Ádám Mann, Kalliopi Mastoraki, SeoJeong Moon, Maja Nisevic, Balázs Pejó, Kostas Papagiannopoulos, Vassilis Paliouras, Paolo Palmieri, Francesca Palumbo, Juan Carlos Pérez Baun, Péter Pollner, Eduard Porta-Pardo, Luca Pulina, Muhammad Ali Siddiqi, Daniela Spajic, Christos Strydis, Georgios Tasopoulos, Vincent Thouvenot, Christos Tselios, Apostolos P. Fournaris
SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space. DATE (2024)
Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis
A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity. IEEE Trans. Emerg. Top. Comput. 12 (2) (2024)
Thodoris Spanos, Fran Fabra, José A. Lopez-Salcedo, Gonzalo Seco-Granados, Nikos Kanistras, Ivan Lapin, Vassilis Paliouras
Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios. WIPHAL (2024)
Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis
An end-to-end RNS CNN Accelerator. AICAS (2024)
Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, George C. Alexandropoulos
Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case. ICC Workshops (2023)
Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. ICCAD (2023)
Emmanouil Kavvousanos, Vasilis Sakellariou, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization. ARITH (2023)
Emmanouil Kavvousanos, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights. ICECS (2023)
Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
Modified Logarithmic Multiplication Approximation for Machine Learning. AICAS (2023)
Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis
A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity. ARITH (2023)
Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras
Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications. ICASSP (2023)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Path-Based Delay Variation Models for Parallel-Prefix Adders. IEEE Trans. Emerg. Top. Comput. 11 (3) (2023)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. IEEE Trans. Emerg. Top. Comput. 11 (4) (2023)
Thodoris Spanos, Vassilis Paliouras
Hardware Aspects of Iterative Receivers for V2X Applications. MOCAST (2022)
Alexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras
High-Level Synthesis design approach for Number-Theoretic Multiplier. VLSI-SoC (2022)
E. Kavvousanos, Vassilis Paliouras
A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation. MOCAST (2022)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. ISCAS (2022)
Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis
A High-performance RNS LSTM block. ISCAS (2022)
Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras
Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods. MOCAST (2022)
Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras
High-Level Synthesis design approach for Number-Theoretic Transform Implementations. VLSI-SoC (2021)
Dimitris Chytas, Vassilis Paliouras
A 5G-code based iterative Non-Binary LDPC decoder. ICECS (2021)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. ARITH (2021)
Ioannis Kouretas, Vassilis Paliouras
Hardware Aspects of Parallel Neural Network Implementation. MOCAST (2021)
Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
A Novel Stochastic Polar Architecture for All-Digital Transmission. ISCAS (2021)
Ioannis Kouretas, Vassilis Paliouras
Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference. ISCAS (2021)
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Dimitris Vordonis, Vassilis Paliouras
Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels. IEEE Open J. Commun. Soc. 2 (2021)
Vasilis Sakellariou, Vassilis Paliouras
An FPGA Accelerator for Spiking Neural Network Simulation and Training. ISCAS (2021)
Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
E. Kavvousanos, Vassilis Paliouras
Optimizing Deep Learning Decoders for FPGA Implementation. FPL (2021)
Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis
On Reducing the Number of Multiplications in RNS-based CNN Accelerators. ICECS (2021)
E. Kavvousanos, Vassilis Paliouras
An Iterative Approach to Syndrome-based Deep Learning Decoding. GLOBECOM (Workshops) (2020)
Dimitris Chytas, Vassilis Paliouras
Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders. ICECS (2020)
Kleanthis Papachatzopoulos, Chris Andriakopoulos, Vassilis Paliouras
Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. ISCAS (2020)
Mark G. Arnold, Vassilis Paliouras, Ioannis Kouretas
Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation. IEEE Trans. Computers 69 (12) (2020)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. ARITH (2020)
Konstantina Karagianni, Vassilis Paliouras
Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation. ICECS (2019)
E. Kavvousanos, Vassilis Paliouras
Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes. NORCAS (2019)
Ioannis Kouretas, Vassilis Paliouras
Simplified Hardware Implementation of the Softmax Activation Function. MOCAST (2019)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Ioannis Kouretas, Vassilis Paliouras
Radix-3 low-complexity modulo-M multipliers. PATMOS (2019)
Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, John R. Cowles
Under- and Overflow Detection in the Residue Logarithmic Number System. ARITH (2019)
Dimitris Vordonis, Vassilis Paliouras
Sphere Decoder for Massive MIMO Systems. NORCAS (2019)
Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, Austin Morgan
One-Hot Residue Logarithmic Number Systems. PATMOS (2019)
Panagiotis Sakellariou, Vassilis Paliouras
Reconfigurable RO-Path Delay Sensor. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Andreas Kalampoukas, Vassilis Paliouras
A novel algorithm and hardware architecture for low-complexity soft demappers. MOCAST (2018)
Ioannis Kouretas, Vassilis Paliouras
Hardware aspects of Long Short Term Memory. ICECS (2018)
Ioannis Kouretas, Vassilis Paliouras
Logarithmic number system for deep learning. MOCAST (2018)
E. Kavvousanos, Vassilis Paliouras, Ioannis Kouretas
Simplified Deep-Learning-based decoders for linear block codes. ICECS (2018)
Ioannis Tsatsaragkos, Vassilis Paliouras
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Vassilis Paliouras, Konstantina Karagianni, Yann Oster
Low-cost soft-error compensation for transposed FIR digital filters. MOCAST (2018)
Christos Andriakopoulos, Vassilis Paliouras
Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder. MOCAST (2018)
Vassilis Paliouras, Konstantina Karagianni, Yann Oster
Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. PATMOS (2018)
Kleanthis Papachatzopoulos, Vassilis Paliouras
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Giorgos Tsiaras, Vassilis Paliouras
Multi-operand logarithmic addition/subtraction based on Fractional Normalization. MOCAST (2017)
Giorgos Tsiaras, Vassilis Paliouras
Logarithmic number system addition-subtraction using fractional normalization. ISCAS (2017)
Georgios Perris-Samios, Vassilis Paliouras
An approximate hardware check node for λ-min-based LDPC decoders. EUSIPCO (2017)
Alexios Thanos, Vassilis Paliouras
Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method. MOCAST (2017)
Nikolaos M. Avouris, Kyriakos N. Sgarbas, Vassilis Paliouras, Michalis Koukias
Work in progress: An introduction to computing course using a Python-based experiential approach. EDUCON (2017)
Panagiotis Sakellariou, Vassilis Paliouras
Application-Specific Low-Power Multipliers. IEEE Trans. Computers 65 (10) (2016)
Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras
Dynamic delay variation behaviour of RNS multiply-add architectures. ISCAS (2016)
Ioannis Tsatsaragkos, Vassilis Paliouras
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Ahmed Mahdi, Vassilis Paliouras
On the Encoding Complexity of Quasi-Cyclic LDPC Codes. IEEE Trans. Signal Process. 63 (22) (2015)
Christos Vasilopoulos, Vassilis Paliouras
A technique for the identification of trapping sets in LDPC codes. ICECS (2014)
Ahmed Mahdi, Vassilis Paliouras
A Low Complexity-High Throughput QC-LDPC Encoder. IEEE Trans. Signal Process. 62 (10) (2014)
P. Mermigkas, Vassilis Paliouras
Effective sum of squares implementation for BPSK soft-decision decoding. ICECS (2014)
Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras
Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters. IEEE Trans. Computers 62 (11) (2013)
Nikos Kanistras, Vassilis Paliouras
A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm. SiPS (2013)
Ioannis Kouretas, Vassilis Paliouras
Delay-variation-tolerant FIR filter architectures based on the Residue Number System. ISCAS (2013)
Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. SiPS (2012)
Ahmed Mahdi, Vassilis Paliouras
Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders. SiPS (2012)
Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. ICECS (2012)
G. Spourlis, Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
Error Floor Compensation for LDPC Codes Using Concatenated Schemes. SiPS (2012)
Ioannis Kouretas, Vassilis Paliouras
Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation. ISCAS (2012)
Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. ICSAMOS (2012)
Panagiotis Sakellariou, Vassilis Paliouras
Low-power two's-complement multiplication based on selective activation. ICECS (2012)
Panagiotis Sakellariou, Vassilis Paliouras
Low-Power Delay Sensors on FPGAs. PATMOS (2012)
Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
Multiple LDPC decoder of very low bit-error rate. DSP (2011)
Ioannis Tsatsaragkos, Vassilis Paliouras
A flexible layered LDPC decoder. ISWCS (2011)
Ioannis Paraskevakos, Vassilis Paliouras
A flexible high-throughput hardware architecture for a gaussian noise generator. ICASSP (2011)
Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras
A Residue Logarithmic Number System ALU using interpolation and cotransformation. ASAP (2011)
Nikos Kanistras, Vassilis Paliouras
Impact of Approximation Error on the Decisions of LDPC Decoding. J. Signal Process. Syst. 64 (1) (2011)
Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
A syndrome-based LDPC decoder with very low error floor. DSP (2011)
Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras
An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes. SiPS (2011)
E. Theodorakis, Vassilis Paliouras
On the impact of encoding on the complexity of residue arithmetic circuits. ICECS (2011)
Rodoula Makri, Petros Tsenes, Dimitrios Economou, Yannis Papananos, Dimitrios Dervenis, Michael K. Birbas, John C. Kikidis, Vassilis Paliouras, Grigorios Kalivas, Alexios N. Birbas, Panos Karaivazoglou, Yorgos Stratakos, John Korinthios, Stelios Siskos, Alkis A. Hatzopoulos, John Komninos, Serafeim Katsikas, Konstantinos N. Voudouris, Andreas Rigas, George Agapiou, Polivios Raxis
Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration. ICECS (2011)
Mark G. Arnold, John R. Cowles, Vassilis Paliouras, Ioannis Kouretas
Towards a Quaternion Complex Logarithmic Number System. IEEE Symposium on Computer Arithmetic (2011)
Andreas Brokalakis, Vassilis Paliouras
Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems. SiPS (2011)
Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis
Digital baseband challenges for a 60GHz gigabit link. ICECS (2011)
Ioannis Kouretas, Vassilis Paliouras
Residue Arithmetic for Designing Low-Power Multiply-Add Units. PATMOS (2010)
Ioannis Kouretas, Vassilis Paliouras
Residue arithmetic bases for reducing delay variation. ISCAS (2010)
Ioannis Kouretas, Vassilis Paliouras
RNS multi-voltage low-power multiply-add unit. ICECS (2010)
Angelos Spanos, Vassilis Paliouras
VLSI implementation and performance of turbo decoding stopping criteria. ICECS (2010)
Ioannis Kouretas, Vassilis Paliouras
A Low-Complexity High-Radix RNS Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2009)
Theodoros Giannopoulos, Vassilis Paliouras
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. J. Signal Process. Syst. 56 (2-3) (2009)
Ioannis Kouretas, Vassilis Paliouras
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. PATMOS (2009)
Ioannis Kouretas, Vassilis Paliouras
Variation-tolerant Design Using Residue Number System. DSD (2009)
Ioannis Kouretas, Vassilis Paliouras
High-radix residue arithmetic bases for low-power DSP systems. DPS (2009)
Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras
Low-power logarithmic number system addition/subtraction and their impact on digital filters. ISCAS (2008)
Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis
A frequency-domain interpolation implementation for OFDM transmitters. ISWPC (2008)

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Publication Activity (10 Years)

Top Topics

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Vassilis Paliouras