Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes.
E. KavvousanosVassilis PaliourasPublished in: NORCAS (2019)
Keyphrases
- hardware implementation
- reed solomon
- neural network
- fpga implementation
- error correction
- signal processing
- efficient implementation
- error control
- image processing algorithms
- distributed video coding
- software implementation
- hardware design
- field programmable gate array
- dedicated hardware
- low complexity
- hardware architecture
- pipeline architecture
- parallel architecture
- pattern recognition
- joint source channel
- turbo codes
- error concealment
- image compression
- general purpose
- motion estimation
- image binarization
- image processing
- computer vision