A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation.
E. KavvousanosVassilis PaliourasPublished in: MOCAST (2022)
Keyphrases
- fpga implementation
- deep learning
- low latency
- hardware implementation
- unsupervised learning
- high throughput
- high speed
- machine learning
- real time
- field programmable gate array
- highly efficient
- mental models
- weakly supervised
- virtual machine
- image processing algorithms
- efficient implementation
- general purpose
- data sets
- transfer function
- operating system
- pattern recognition
- image segmentation