Ioannis Tsatsaragkos

Publication Activity (10 Years)

Years Active: 2011-2018
Publications (10 Years): 2

Top Topics

Low Density Parity Check

Error Correction

Hardware Implementation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Ioannis Tsatsaragkos, Vassilis Paliouras
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Ioannis Tsatsaragkos, Vassilis Paliouras
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. SiPS (2012)
Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. ICECS (2012)
G. Spourlis, Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
Error Floor Compensation for LDPC Codes Using Concatenated Schemes. SiPS (2012)
Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. ICSAMOS (2012)
Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
Multiple LDPC decoder of very low bit-error rate. DSP (2011)
Ioannis Tsatsaragkos, Vassilis Paliouras
A flexible layered LDPC decoder. ISWCS (2011)
Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
A syndrome-based LDPC decoder with very low error floor. DSP (2011)
Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis
Digital baseband challenges for a 60GHz gigabit link. ICECS (2011)