An approximate hardware check node for λ-min-based LDPC decoders.

Georgios Perris-Samios Vassilis Paliouras

Published in: EUSIPCO (2017)

Keyphrases

decoding algorithm
low cost
hardware and software
error detection
real time
hardware architecture
ldpc codes
image processing
hardware implementation
vlsi architecture
computer systems
tree structure
graph structure
error correction
power reduction