Dimitris Nikolos

Publication Activity (10 Years)

Years Active: 1984-2024
Publications (10 Years): 10

Top Venues

DATE

ISQED

IOLTS

EDCC

Publications

Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
Improving the Performance Predictability of Faulty Data Caches. EDCC (2024)
Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
Enabling efficient sub-block disabled caches using coarse grain spatial predictions. Microprocess. Microsystems 90 (2022)
Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
Run Time Management of Faulty Data Caches. ETS (2021)
Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos
A novel fault tolerant cache architecture based on orthogonal latin squares theory. DATE (2018)
Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos
Recovery of performance degradation in defective branch target buffers. IOLTS (2016)
Panagiotis Sismanoglou, Dimitris Nikolos
Low capture power dictionary-based test data compression. ISQED (2016)
Panagiotis Sismanoglou, Dimitris Nikolos
Conditional soft-edge flip-flop for SET mitigation. IOLTS (2016)
Panagiotis Sismanoglou, Vlasis Pitsios, Dimitris Nikolos
Preemptive built-in self-test for in-field structural testing. ISQED (2015)
Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems. DATE (2015)
Michail Mavropoulos, Georgios Keramidas, Grigorios Adamopoulos, Dimitris Nikolos
Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems. ACM Great Lakes Symposium on VLSI (2015)
Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos
Spatial pattern prediction based management of faulty data caches. DATE (2014)
Panagiotis Sismanoglou, Dimitris Nikolos
Test data compression based on reuse and bit-flipping of parts of dictionary entries. DDECS (2014)
Panagiotis Sismanoglou, Dimitris Nikolos
Enhancing dictionary based test data compression using the ATE repeat instruction. ICECS (2013)
Panagiotis Sismanoglou, Dimitris Nikolos
Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Panagiotis Sismanoglou, Dimitris Nikolos
Test data compression based on the reuse of parts of the dictionary entries. ICECS (2011)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Dimitris Nikolos, Dimitrios Kagaris, Samara Sudireddy, Spyros Gidaros
An Improved Search Method for Accumulator-Based Test Set Embedding. IEEE Trans. Computers 58 (1) (2009)
M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
LFSR-based test-data compression with self-stoppable seeds. DATE (2009)
Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers 56 (8) (2007)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
Sorter Based Permutation Units for Media-Enhanced Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Efficient test-data compression for IP cores using multilevel Huffman coding. DATE (2006)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED (2006)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
Fast bit permutation unit for media enhanced microprocessors. ISCAS (2006)
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
An Energy-Delay Efficient Subword Permutation Unit. ASAP (2006)
Dimitris Bakalis, Kostas Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52 (1) (2006)
Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros
Diophantine-Equation Based Arithmetic Test Set Embedding. IOLTS (2006)
Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos
Power aware test-data compression for scan-based testing. ICECS (2005)
Giorgos Dimitrakopoulos, Dimitris Nikolos
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. PATMOS (2005)
Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos
Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED (2005)
Maciej Bellos, Dimitris Nikolos
Deterministic Test Vector Compression / Decompression Using an Embedded Processor. EDCC (2005)
Giorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
New architectures for modulo 2N - 1 adders. ICECS (2005)
Giorgos Dimitrakopoulos, Dimitris Nikolos
High-Speed Parallel-Prefix VLSI Ling Adders. IEEE Trans. Computers 54 (2) (2005)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54 (4) (2005)
Costas Laoudias, Dimitris Nikolos
A new test pattern generator for high defect coverage in a BIST environment. ACM Great Lakes Symposium on VLSI (2004)
Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS (2004)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (10) (2004)
Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED (2004)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
-1 Multipliers. IEEE Trans. Computers 53 (3) (2004)
Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI (2004)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53 (9) (2004)
Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
Scan Cell Ordering for Low Power BIST. ISVLSI (2004)
P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos
Accumulator based Test-per-Scan BIST. IOLTS (2004)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
+1 tree multipliers for diminished-1 operands. ICECS (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
An Efficient BIST scheme for High-Speed Adders. IOLTS (2003)
Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP (2003)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52 (7) (2003)
Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
Low Power Test Set Embedding Based on Phase Shifters. ISVLSI (2003)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI (2003)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52 (11) (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
Efficient BIST schemes for RNS datapaths. ISCAS (5) (2003)
Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
- 1 adders. ISCAS (5) (2003)
Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos
Test Set Embedding Based on Phase Shifters. EDCC (2002)
Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW (2002)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. 18 (3) (2002)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Ling adders in CMOS standard cell technologies. ICECS (2002)
Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
A new technique for IDDQ testing in nanometer technologies. Integr. 31 (2) (2002)
Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. 48 (4-5) (2002)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW (2002)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium (2002)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED (2002)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED (2002)
Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra
Guest Editorial. J. Electron. Test. 18 (3) (2002)
Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
+1 Adder Design. IEEE Trans. Computers 51 (12) (2002)
Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 2001 (3) (2001)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW (2001)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
±1 adders. ICECS (2001)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW (2001)
Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic (2001)
Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED (2001)
Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, D. Lymperopoulos
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. IEEE International Workshop on Rapid System Prototyping (2001)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI (2001)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW (2001)
Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED (2000)
Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49 (7) (2000)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC (2000)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
A Compact Built-In Current Sensor for IDDQ Testing. IOLTW (2000)
Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
Codes. VLSI Design 2000 (1) (2000)
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE (2000)
Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
On Testability of Multiple Precharged Domino Logic. ISQED (2000)
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE (1999)
A. Vasilliou, K. Gounaris, Kostas Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. IEEE International Workshop on Rapid System Prototyping (1999)
Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis
An Accumulator-Based BIST Approach for Two-Pattern Testing. J. Electron. Test. 15 (3) (1999)
Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis
New efficient totally self-checking Berger code checkers. Integr. 28 (1) (1999)
C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
Design and Analysis of On-Chip CPU Pipelined Caches. VLSI (1999)
Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI (1999)
Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos
Path delay fault testing of Benes multistage interconnection networks. ICECS (1999)
Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC (1999)
Xrysovalantis Kavousianos, Dimitris Nikolos
Modular TSC Checkers for Bose-Lin and Bose Codes. VTS (1999)
Dimitris Nikolos, Haridimos T. Vergos
On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers 48 (10) (1999)
Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT (1999)
G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium (1999)

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Publication Activity (10 Years)

Top Topics

Top Venues

Dimitris Nikolos