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Efficient partial scan cell gating for low-power scan-based testing.

Xrysovalantis KavousianosDimitris BakalisDimitris Nikolos
Published in: ACM Trans. Design Autom. Electr. Syst. (2009)
Keyphrases
  • low power
  • power consumption
  • high speed
  • low cost
  • single chip
  • high power
  • digital signal processing
  • vlsi circuits
  • logic circuits
  • vlsi architecture
  • real time
  • gate array