Xrysovalantis Kavousianos

Publication Activity (10 Years)

Years Active: 1997-2019
Publications (10 Years): 6

Top Topics

Error Tolerance

Optimization Process

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Computers

Publications

Panagiotis Georgiou, Iakovos Theodosopoulos, Xrysovalantis Kavousianos
K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing. ETS (2019)
Panagiotis Georgiou, Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Testing 3D-SoCs Using 2-D Time-Division Multiplexing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Panagiotis Georgiou, Xrysovalantis Kavousianos, Riccardo Cantoro, Matteo Sonza Reorda
Fault-Independent Test-Generation for Software-Based Self-Testing. IOLTS (2018)
Fotios Vartziotis, Xrysovalantis Kavousianos
Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage. DATE (2017)
Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty
SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (11) (2017)
Panagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Two-dimensional time-division multiplexing for 3D-SoCs. ETS (2016)
Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Fotios Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty
Test-access-mechanism optimization for multi-Vdd SoCs. ITC (2015)
Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs. ETS (2015)
Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE (2014)
Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Recent advances in single- and multi-site test optimization for DVS-based SoCs. DTIS (2014)
Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63 (5) (2014)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Testing for SoCs with advanced static and dynamic power-management capabilities. DATE (2013)
Vasileios Tenentes, Xrysovalantis Kavousianos
High-Quality Statistical Test Compression With Narrow ATE Interface. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. ETS (2012)
Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. ETS (2011)
Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium (2011)
Vasileios Tenentes, Xrysovalantis Kavousianos
Low Power Test-Compression for High Test-Quality and Low Test-Data Volume. Asian Test Symposium (2011)
Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
A BIST scheme for testing and repair of multi-mode power switches. IOLTS (2011)
Vasileios Tenentes, Xrysovalantis Kavousianos
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. ICCAD (2011)
Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design (2011)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros
Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros, Vasileios Tenentes
Defect Coverage-Driven Window-Based Test Compression. Asian Test Symposium (2010)
S. Balatsouka, Vasileios Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Defect aware X-filling for low-power scan testing. DATE (2010)
Vasileios Tenentes, Xrysovalantis Kavousianos
Self-Freeze Linear Decompressors for Low Power Testing. ISVLSI (2010)
Vasileios Tenentes, Xrysovalantis Kavousianos
Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing. ISVLSI (Selected papers) (2010)
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Generation of compact test sets with high defect coverage. DATE (2009)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
LFSR-based test-data compression with self-stoppable seeds. DATE (2009)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos
Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) (2008)
Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. DATE (2008)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers 56 (8) (2007)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
Efficient test-data compression for IP cores using multilevel Huffman coding. DATE (2006)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED (2006)
George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos
Power aware test-data compression for scan-based testing. ICECS (2005)
Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos
Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED (2005)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (10) (2004)
Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED (2004)
Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI (2004)
Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) (2003)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI (2003)
Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC (2003)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. 18 (3) (2002)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium (2002)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED (2002)
Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 2001 (3) (2001)
Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED (2001)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI (2001)
Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW (2001)
Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW (2001)
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC (2000)
Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
Codes. VLSI Design 2000 (1) (2000)
Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis
New efficient totally self-checking Berger code checkers. Integr. 28 (1) (1999)
Xrysovalantis Kavousianos, Dimitris Nikolos
Modular TSC Checkers for Bose-Lin and Bose Codes. VTS (1999)
Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT (1999)
Xrysovalantis Kavousianos, Dimitris Nikolos
Novel Single and Double Output TSC Berger Code Checkers. VTS (1998)
Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT (1997)
Xrysovalantis Kavousianos, Dimitris Nikolos
Self-exercising self testing k-order comparators. VTS (1997)