Stanislaw J. Piestrak

ORCID

Publication Activity (10 Years)

Years Active: 1987-2023
Publications (10 Years): 10

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

LASCAS

Circuits Syst. Signal Process.

DSD

Technical University of Wroclaw, Poland (PHD)

Education History

Technical University of Wroclaw, Poland

PHD

Publications

Piotr Patronik, Stanislaw J. Piestrak
+ 1}. EURASIP J. Adv. Signal Process. 2023 (1) (2023)
Piotr Patronik, Stanislaw J. Piestrak
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels. J. Signal Process. Syst. 90 (3) (2018)
Piotr Patronik, Stanislaw J. Piestrak
Even). Circuits Syst. Signal Process. 37 (11) (2018)
Piotr Patronik, Stanislaw J. Piestrak
Design of residue generators with CLA/compressor trees and multi-bit EAC. LASCAS (2017)
Piotr Patronik, Stanislaw J. Piestrak
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Piotr Patronik, Stanislaw J. Piestrak
Even). Circuits Syst. Signal Process. 36 (11) (2017)
Piotr Patronik, Stanislaw J. Piestrak
Design of a low-power RNS-enhanced arithmetic unit. LASCAS (2016)
B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS (2015)
Stanislaw J. Piestrak
A note on RNS architectures for the implementation of the diagonal function. Inf. Process. Lett. 115 (4) (2015)
Stanislaw J. Piestrak, Piotr Patronik
Fault-tolerant implementation of direct FIR filters protected using residue codes. NORCAS (2015)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Piotr Patronik, Stanislaw J. Piestrak
odd). IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38 (2) (2014)
Stanislaw J. Piestrak, Piotr Patronik
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. DSD (2014)
Piotr Patronik, Stanislaw J. Piestrak
-1} (n even). IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC (2014)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD (2013)
Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62 (6) (2013)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC (2013)
Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava
Design of an RNS reverse converter for a new five-moduli special set. ACM Great Lakes Symposium on VLSI (2012)
Stanislaw J. Piestrak
Design of multi-residue generators using shared logic. ISCAS (2011)
Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava
Fast and energy-efficient constant-coefficient FIR filters using residue number system. ISLPED (2011)
Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Error recovery technique for coarse-grained reconfigurable architectures. DDECS (2011)
Stanislaw J. Piestrak
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. DSD (2010)
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14 (8) (2010)
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs (10) (2010)
Stanislaw J. Piestrak
-1. ISCAS (2010)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Design of a fault-tolerant coarse-grained. ISQED (2010)
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak
Exploiting residue number system for power-efficient digital signal processing in embedded processors. CASES (2009)
Houssein Jaber, Fabrice Monteiro, Stanislaw J. Piestrak, Abbas Dandache
Design of parallel fault-secure encoders for systematic cyclic block transmission codes. Microelectron. J. 40 (12) (2009)
Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. IOLTS (2007)
Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel
Characterizing Laser-Induced Pulses in ICs: Methodology and Results. IOLTS (2006)
Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache
Modeling of Transients Caused by a Laser Attack on Smart Cards. IOLTS (2005)
Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
Designing fault-secure parallel encoders for systematic linear error correcting codes. IEEE Trans. Reliab. 52 (4) (2003)
Stanislaw J. Piestrak
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes. IEEE Trans. Computers 51 (2) (2002)
Stanislaw J. Piestrak
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. IEEE Trans. Computers 51 (6) (2002)
Stanislaw J. Piestrak
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. DFT (2002)
Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. DFT (2001)
Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW (2001)
Jerzy W. Greblicki, Stanislaw J. Piestrak
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. EDCC (1999)
Stanislaw J. Piestrak
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters. J. Electron. Test. 12 (1-2) (1998)
Stanislaw J. Piestrak, Fabrice Pedron, Olivier Sentieys
VLSI implementation and complexity comparison of residue generators modulo 3. EUSIPCO (1998)
Stanislaw J. Piestrak
Membership Test Logic for Delay-Insensitive Codes. ASYNC (1998)
Stanislaw J. Piestrak
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. DFT (1997)
Stanislaw J. Piestrak
Design of Self-Testing Checkers for Borden Codes. IEEE Trans. Computers 45 (4) (1996)
Stanislaw J. Piestrak
Self-Checking Design in Eastern Europe. IEEE Des. Test Comput. 13 (1) (1996)
Stanislaw J. Piestrak
Design of minimal-level PLA self-testing checkers for m-out-of-n codes. IEEE Trans. Very Large Scale Integr. Syst. 4 (2) (1996)
Stanislaw J. Piestrak, Takashi Nanya
Towards Totally Self-Checking Delay-Insensitive Systems. FTCS (1995)
Stanislaw J. Piestrak
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. ICCD (1994)
Stanislaw J. Piestrak
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. ICCD (1994)
Stanislaw J. Piestrak
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. IEEE Trans. Computers 43 (1) (1994)
Stanislaw J. Piestrak
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks. IEEE Trans. Computers 42 (6) (1993)
Stanislaw J. Piestrak
Design of a Self-Testing Checker for Borden Code. ICCD (1991)
Stanislaw J. Piestrak
Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes. Fault-Tolerant Computing Systems (1991)
Stanislaw J. Piestrak
Design of residue generators and multioperand modular adders using carry-save adders. IEEE Symposium on Computer Arithmetic (1991)
Stanislaw J. Piestrak
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. IEEE Trans. Computers 39 (3) (1990)
Stanislaw J. Piestrak
The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes. FTCS (1990)
Stanislaw J. Piestrak
Design of Fast Self-Testing Checkers for a Class of Berger Codes. IEEE Trans. Computers 36 (5) (1987)

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Publication Activity (10 Years)

Top Topics

Top Venues

Stanislaw J. Piestrak