Takashi Nanya

Publication Activity (10 Years)

Years Active: 1978-2012
Publications (10 Years): 0

Top Topics

Ambient Intelligence

Electronic Devices

Top Venues

IEEE Secur. Priv.

Publications

Jean Arlat, Zbigniew Kalbarczyk, Takashi Nanya
Nanocomputing: Small Devices, Large Dependability Challenges. IEEE Secur. Priv. 10 (1) (2012)
Jean Arlat, Cristian Constantinescu, Johan Karlsson, Takashi Nanya, Alan Wood
Introduction to the fifth workshop on dependable and secure nanocomputing. DSN (2011)
Jean Arlat, Cristian Constantinescu, Johan Karlsson, Takashi Nanya, Alan Wood
Introduction to the fifth workshop on dependable and secure nanocomputing. DSN Workshops (2011)
Masashi Imai, Tomohide Nagai, Takashi Nanya
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. DSN Workshops (2010)
James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. PRDC (2010)
Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ISCAS (2010)
Roberto Jung Drebes, Takashi Nanya
Analysis of Inter-Module Error Propagation Paths in Monolithic Operating System Kernels. EDCC (2010)
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
N-way ring and square arbiters. ICCD (2009)
Roberto Jung Drebes, Takashi Nanya
Zapmem: A Framework for Testing the Effect of Memory Corruption Errors on Operating System Kernel Reliability. PRDC (2009)
Wenyu Qu, Masaru Kitsuregawa, Yanming Shen, Takashi Nanya
An optimal lifetime-adaptive method for wireless sensor networks. Comput. Syst. Sci. Eng. 24 (3) (2009)
Masashi Imai, Kouei Takada, Takashi Nanya
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. ASYNC (2009)
Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. ICDM Workshops (2008)
Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD (2008)
Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. PRDC (2008)
Bogdan Tomoyuki Nassu, Takashi Nanya
Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. ISAS (2008)
Bogdan Tomoyuki Nassu, Kiyonobu Uehara, Takashi Nanya
Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. EDCC (2008)
Masashi Imai, Takashi Nanya
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD (2008)
Roberto Jung Drebes, Takashi Nanya
Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors. PRDC (2008)
Takashi Nanya
Challenges in Dependability of Networked Systems for Information Society. NPC (2007)
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD (2007)
Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Wenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya
An optimal solution for caching multimedia objects in transcoding proxies. Comput. Commun. 30 (8) (2007)
Bogdan Tomoyuki Nassu, Takashi Nanya, Elias P. Duarte Jr.
Topology Discovery in Dynamic and Decentralized Networks with Mobile Agents and Swarm Intelligence. ISDA (2007)
Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE (2007)
Wenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya
An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks. ICC (2007)
Keqiu Li, Takashi Nanya, Wenyu Qu
Energy Efficient Methods and Techniques for Mobile Computing. SKG (2007)
Keqiu Li, Takashi Nanya, Wenyu Qu
A Minimal Access Cost-Based Multimedia Object Replacement Algorithm. IPDPS (2007)
Keqiu Li, Takashi Nanya, Hong Shen, Francis Y. L. Chin, Weishi Zhang
An efficient cache replacement algorithm for multimedia object caching. Comput. Syst. Sci. Eng. 22 (1-2) (2007)
Keqiu Li, Takashi Nanya, Bo Jiang, Wenyu Qu
State-of-Art Techniques for Object Caching over the Internet. IMSCCS (2) (2006)
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Bogdan Tomoyuki Nassu, Takashi Nanya
A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. PRDC (2006)
Masashi Imai, Takashi Nanya
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC (2006)
Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT (2006)
Wenyu Qu, Keqiu Li, Hong Shen, Yingwei Jin, Takashi Nanya
The Cache Replacement Problem for Multimedia Object Caching. SKG (2005)
Keqiu Li, Wenyu Qu, Hong Shen, Di Wu, Takashi Nanya
Two Cache Replacement Algorithms Based on Association Rules and Markov Models. SKG (2005)
Masashi Imai, Metehan Özcan, Takashi Nanya
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC (2004)
Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS (2004)
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD (2004)
Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) (2003)
Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE (2003)
Euiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. ASP-DAC (2003)
Wen Gao, Xinyu Liu, Lei Wang, Takashi Nanya
A Reconfigurable High Availability Infrastructure in Cluster for Grid. GCC (1) (2003)
Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC (2003)
Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC (2003)
Nattha Sretasereekul, Takashi Nanya
Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2003)
Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) (2003)
Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS (2002)
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS (2002)
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, Takashi Nanya
Design of Asynchronous Controllers with Delay Insensitive Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Metehan Özcan, Masashi Imai, Takashi Nanya
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC (2002)
Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya
An equivalence checking methodology for hardware oriented C-based specifications. HLDVT (2002)
Hiroshi Saito, Alex Kondratyev, Takashi Nanya
Design of Asynchronous Controllers with Delay Insensitive Interface. VLSI Design (2002)
Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC (2001)
Hiroto Kagotani, Takuji Okamoto, Takashi Nanya
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. ASP-DAC (2001)
Nattha Sretasereekul, Takashi Nanya
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ASP-DAC (2001)
Masayuki Tsukisaka, Takashi Nanya
A testable design for asynchronous fine-grain pipeline circuits. PRDC (2000)
Andreas Savva, Takashi Nanya
A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. IEEE Trans. Computers 48 (1) (1999)
Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ASYNC (1998)
Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya
TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC (1998)
Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi
Improving the dependability of network management systems. Int. J. Netw. Manag. 8 (4) (1998)
Arthit Thongtak, Takashi Nanya
Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Systems and Computers in Japan 29 (2) (1998)
Elias Procópio Duarte Jr., Takashi Nanya
A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. IEEE Trans. Computers 47 (1) (1998)
Mohit Sahni, Takashi Nanya
On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. ASP-DAC (1998)
Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi
Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis. Integrated Network Management (1997)
Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya
Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28 (8-9) (1997)
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD (1997)
Hiroto Kagotani, Takashi Nanya
Performance enhancement of two-phase quasi-delay-insensitive circuits. Systems and Computers in Japan 27 (5) (1996)
Masaaki Maezawa, Itaru Kurosawa, Yoshio Kameda, Takashi Nanya
Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits. ASYNC (1996)
Sung-Bum Park, Takashi Nanya
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. VLSI Design (1996)
Elias Procópio Duarte Jr., Takashi Nanya
An SNMP-based implementation of the adaptive distributed system-level diagnosis algorithm for LAN fault management. NOMS (1996)
Elias Procópio Duarte Jr., Takashi Nanya
Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management. SRDS (1996)
Ryuichi Takahashi, Takashi Nanya
Logic circuit design for testability using orthonormal expansions. Systems and Computers in Japan 26 (11) (1995)
Stanislaw J. Piestrak, Takashi Nanya
Towards Totally Self-Checking Delay-Insensitive Systems. FTCS (1995)
Andreas Savva, Takashi Nanya
Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory. FTCS (1995)
Hiroto Kagotani, Takashi Nanya
Synthesis of two-phase quasi-delay-insensitive circuits from dependency graphs. Systems and Computers in Japan 26 (4) (1995)
Yasuo Tan, Takashi Nanya
A fault-tolerant multilayer neural network model and its properties. Systems and Computers in Japan 25 (2) (1994)
Masashi Kuwako, Takashi Nanya
Timing-reliability evaluation of asynchronous circuits based on different delay models. ASYNC (1994)
Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. IEEE Des. Test Comput. 11 (2) (1994)
Takashi Nanya, Shin'ichi Hatakenaka, Ryuichi Onoo
Design of Fully Exercised SFS/SCD Logic Networks. FTCS (1992)
Takashi Nanya, Masatoshi Uchida
A strongly fault-secure and strongly code-disjoint realization of combinational circuits. FTCS (1989)
Takashi Nanya, Hendrik A. Goosen
The Byzantine hardware fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (11) (1989)
Atsushi Takahara, Takashi Nanya
A higher level hardware design verification. ICCD (1988)
Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya
Test research in Japan. IEEE Des. Test 5 (5) (1988)
Takashi Nanya, Samiha Mourad, Edward J. McCluskey
Multiple stuck-at fault testability of self-testing checkers. FTCS (1988)
Takashi Nanya, Toshiaki Kawamura
Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. IEEE Trans. Computers 37 (1) (1988)
Takashi Nanya, Toshiaki Kawamura
A Note on Strongly Fault-Secure Sequential Circuits. IEEE Trans. Computers 36 (9) (1987)
Takashi Nanya, Toshiaki Kawamura
On Error Indication for Totally Self-Checking Systems. IEEE Trans. Computers 36 (11) (1987)
Takashi Nanya, Toshiaki Kawamura
Error-secure and error-propagating concepts for strongly fault-secure systems. Systems and Computers in Japan 18 (3) (1987)
Takashi Nanya, Toshiaki Kawamura
A design approach to self-checking processors. Systems and Computers in Japan 17 (10) (1986)
Teruhiko Yamada, Takashi Nanya
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. IEEE Trans. Computers 33 (8) (1984)
Teruhiko Yamada, Takashi Nanya
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". IEEE Trans. Computers 32 (5) (1983)
Takashi Nanya, Yoshihiro Tohma
Universal Multicode STT State Assignments for Asynchronous Sequential Machines. IEEE Trans. Computers 28 (11) (1979)
Takashi Nanya, Yoshihiro Tohma
On Universal Single Transition Time Asynchronous State Assignments. IEEE Trans. Computers 27 (8) (1978)