Teruhiko Yamada

Publication Activity (10 Years)

Years Active: 1983-1999
Publications (10 Years): 0

Publications

Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. Asian Test Symposium (1999)
Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. Asian Test Symposium (1998)
Teruhiko Yamada
1997 Asian Test Symposium. IEEE Des. Test Comput. 15 (1) (1998)
Koji Yamazaki, Teruhiko Yamada
An approach to diagnose logical faults in partially observable sequential circuits. Asian Test Symposium (1997)
Teruhiko Yamada, Tsuyoshi Sasaki
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. Asian Test Symposium (1996)
Teruhiko Yamada
Accelerating the Pace of R&D in Asia. IEEE Des. Test Comput. 12 (3) (1995)
Koji Yamazaki, Teruhiko Yamada
A Single Bridging Fault Location Technique for CMOS Combinational Circuits. IEICE Trans. Inf. Syst. (7) (1995)
Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium (1995)
Teruhiko Yamada, Yoshiyuki Nakamura
A method of diagnosing single stuck-at faults in combinational circuits. Systems and Computers in Japan 23 (14) (1992)
Teruhiko Yamada, Koji Yamazaki
Method of diagnosing single bridging faults in combinational circuit. Systems and Computers in Japan 22 (9) (1991)
Teruhiko Yamada, Shuji Hamada, Tatsuo Matsumoto, Toshihiko Takahashi, Takao Nakayama
Method of diagnosing multiple stuck-at-faults in combinational circuits. Systems and Computers in Japan 22 (11) (1991)
Teruhiko Yamada, Hiroshi Nakajima
Pseudorandom pattern built-in self-test for embedded rams. Systems and Computers in Japan 21 (12) (1990)
Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya
Test research in Japan. IEEE Des. Test 5 (5) (1988)
Teruhiko Yamada
Syndrome-testable design and syndrome computing method for large PLA's. Systems and Computers in Japan 17 (4) (1986)
Yoshiyuki Koseki, Teruhiko Yamada
PLAYER: a PLA design system for VLSI's. DAC (1985)
Teruhiko Yamada, Takashi Nanya
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. IEEE Trans. Computers 33 (8) (1984)
Teruhiko Yamada
Syndrome-Testable Design of Programmable Logic Arrays. ITC (1983)
Teruhiko Yamada, Takashi Nanya
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". IEEE Trans. Computers 32 (5) (1983)