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A Single Bridging Fault Location Technique for CMOS Combinational Circuits.
Koji Yamazaki
Teruhiko Yamada
Published in:
IEICE Trans. Inf. Syst. (1995)
Keyphrases
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delay insensitive
high speed
circuit design
analog vlsi
vlsi circuits
asynchronous circuits
neural network
low cost
fault diagnosis
logic circuits
low power
genetic algorithm
fault models
real time
data sets
power dissipation