Edward J. McCluskey

Publication Activity (10 Years)

Years Active: 1957-2016
Publications (10 Years): 1

Top Venues

IEEE Trans. Computers

Publications

Paolo Montuschi, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto
State of the Journal. IEEE Trans. Computers 65 (7) (2016)
Ahmad A. Al-Yamani, Edward J. McCluskey
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. J. Electron. Test. 26 (5) (2010)
Jaekwang Lee, Intaik Park, Edward J. McCluskey
Error Sequence Analysis. VTS (2008)
Intaik Park, Edward J. McCluskey
Launch-on-Shift-Capture Transition Tests. ITC (2008)
Jaekwang Lee, Edward J. McCluskey
Failing Frequency Signature Analysis. ITC (2008)
Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey
Inconsistent Fail due to Limited Tester Timing Accuracy. VTS (2008)
François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh
How Many Test Patterns are Useless? VTS (2008)
Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
California scan architecture for high quality and low power testing. ITC (2007)
Kyoung Youn Cho, Edward J. McCluskey
Test Set Reordering Using the Gate Exhaustive Test Metric. VTS (2007)
Erik Chmelar, Edward J. McCluskey
Session Abstract. VTS (2006)
François-Fabien Ferhani, Edward J. McCluskey
Classifying Bad Chips and Ordering Test Sets. ITC (2006)
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
Optimized reseeding by seed ordering and encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (2) (2005)
Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
Gate exhaustive testing. ITC (2005)
Ahmad A. Al-Yamani, Edward J. McCluskey
BIST-Guided ATPG. ISQED (2005)
Chien-Mo James Li, Edward J. McCluskey
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Ahmad A. Al-Yamani, Edward J. McCluskey
Test chip experimental results on high-level structural test. ACM Trans. Design Autom. Electr. Syst. 10 (4) (2005)
Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey
Effective TARO Pattern Generation. VTS (2005)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53 (11) (2004)
Ahmad A. Al-Yamani, Edward J. McCluskey
Test quality for high level structural test. HLDVT (2004)
Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra
Speed Clustering of Integrated Circuits. ITC (2004)
Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS (2004)
Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
Delay Defect Screening using Process Monitor Structures. VTS (2004)
Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra
ELF-Murphy Data on Defects and Test Sets. VTS (2004)
Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey
Reconfigurable Architecture for Autonomous Self-Repair. IEEE Des. Test Comput. 21 (3) (2004)
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
Bist Reseeding with very few Seeds. VTS (2003)
Ahmad A. Al-Yamani, Edward J. McCluskey
Built-In Reseeding for Serial Bist. VTS (2003)
Ahmad A. Al-Yamani, Edward J. McCluskey
Seed encoding with LFSRs and cellular automata. DAC (2003)
Chao-Wen Tseng, James Li, Edward J. McCluskey
Experimental Results for Slow-Speed Testing. VTS (2002)
Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey
ED4I: Error Detection by Diverse Data and Duplicated Instructions. IEEE Trans. Computers 51 (2) (2002)
Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey
Error detection by duplicated instructions in super-scalar processors. IEEE Trans. Reliab. 51 (1) (2002)
Nahmsuk Oh, Edward J. McCluskey
Error detection by selective procedure call duplication for low energy consumption. IEEE Trans. Reliab. 51 (4) (2002)
Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers
Debating the Future of Burn-In. VTS (2002)
Chien-Mo James Li, Edward J. McCluskey
Diagnosis of Sequence-Dependent Chips. VTS (2002)
Subhasish Mitra, Edward J. McCluskey
Dependable Reconfigurable Computing Design Diversity and Self Repair. Evolvable Hardware (2002)
Subhasish Mitra, Edward J. McCluskey, Samy Makar
Design for Testability and Testing of IEEE 1149.1 Tap Controller. VTS (2002)
Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey
Control-flow checking by software signatures. IEEE Trans. Reliab. 51 (1) (2002)
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
Fault Grading FPGA Interconnect Test Configurations. ITC (2002)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51 (5) (2002)
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
Testing Digital Circuits with Constraints. DFT (2002)
Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
Testing for resistive opens and stuck opens. ITC (2001)
Nahmsuk Oh, Edward J. McCluskey
Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. DFT (2001)
Subhasish Mitra, Edward J. McCluskey
Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. VTS (2001)
Shu-Yi Yu, Edward J. McCluskey
On-line testing and recovery in TMR systems for real-time applications. ITC (2001)
Chao-Wen Tseng, Edward J. McCluskey
Multiple-output propagation transition fault test. ITC (2001)
Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT (2001)
Nur A. Touba, Edward J. McCluskey
Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Wei-Je Huang, Edward J. McCluskey
A memory coherence technique for online transient error recovery of FPGA configurations. FPGA (2001)
Shu-Yi Yu, Edward J. McCluskey
Permanent Fault Repair for FPGAs with Limited Redundant Area. DFT (2001)
Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey
Performance Evaluation of Checksum-Based ABFT. DFT (2001)
Subhasish Mitra, Edward J. McCluskey
Design of Redundant Systems Protected Against Common-Mode Failures. VTS (2001)
Chien-Mo James Li, Edward J. McCluskey
Diagnosis of Tunneling Opens. VTS (2001)
Subhasish Mitra, Edward J. McCluskey
Diversity Techniques for Concurrent Error Detection. ISQED (2001)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN (2001)
Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh
MINVDD Testing for Weak CMOS ICs. VTS (2001)
Wei-Je Huang, Edward J. McCluskey
Column-Based Precompiled Configuration Techniques for FPGA. FCCM (2001)
Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson
An Evaluation of Pseudo Random Testing for Detecting Real Defects. VTS (2001)
Subhasish Mitra, Edward J. McCluskey
Combinational logic synthesis for diversity in duplex systems. ITC (2000)
Subhasish Mitra, Edward J. McCluskey
Word Voter: A New Voter Design for Triple Modular Redundant Systems. VTS (2000)
Chien-Mo James Li, Edward J. McCluskey
Testing for tunneling opens. ITC (2000)
Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM (2000)
Subhasish Mitra, Edward J. McCluskey
Which concurrent error detection scheme to choose ? ITC (2000)
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu
Cold Delay Defect Screening. VTS (2000)
Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey
Software-implemented EDAC protection against SEUs. IEEE Trans. Reliab. 49 (3) (2000)
Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey
A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM (2000)
Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey
Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Des. Test Comput. 17 (1) (2000)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
Fault Escapes in Duplex Systems. VTS (2000)
Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
Efficient Multiplexer Synthesis Techniques. IEEE Des. Test Comput. 17 (4) (2000)
Wei-Je Huang, Edward J. McCluskey
Transient errors and rollback recovery in LZ compression. PRDC (2000)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
Common-mode failures in redundant VLSI systems: a survey. IEEE Trans. Reliab. 49 (3) (2000)
Edward J. McCluskey, Chao-Wen Tseng
Stuck-fault tests vs. actual defects. ITC (2000)
Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
A design diversity metric and reliability analysis for redundant systems. ITC (1999)
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
Finite state machine synthesis with concurrent error detection. ITC (1999)
Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
An output encoding problem and a solution technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (6) (1999)
Philip P. Shirvani, Edward J. McCluskey
PADded Cache: A New Fault-Tolerance Technique for Cache Memories. VTS (1999)
Nur A. Touba, Edward J. McCluskey
RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (8) (1999)
Jonathan T.-Y. Chang, Edward J. McCluskey
Detecting resistive shorts for CMOS domino circuits. ITC (1998)
Nirmal R. Saxena, Edward J. McCluskey
Dependable adaptive computing systems-the ROAR project. SMC (1998)
Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ITC (1998)
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey
Experimental Results for IDDQ and VLV Testing. VTS (1998)
Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
Scan Synthesis for One-Hot Signals. ITC (1997)
Samy Makar, Edward J. McCluskey
ATPG for scan chain latches and flip-flops. VTS (1997)
Robert B. Norwood, Edward J. McCluskey
High-Level Synthesis for Orthogonal Sca. VTS (1997)
Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
An output encoding problem and a solution technique. ICCAD (1997)
Jonathan T.-Y. Chang, Edward J. McCluskey
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. VTS (1997)
Nur A. Touba, Edward J. McCluskey
Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Nur A. Touba, Edward J. McCluskey
Pseudo-Random Pattern Testing of Bridging Faults. ICCD (1997)
Nirmal R. Saxena, Edward J. McCluskey
Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 46 (4) (1997)
Jonathan T.-Y. Chang, Edward J. McCluskey
Quantitative analysis of very-low-voltage testing. VTS (1996)
Nur A. Touba, Edward J. McCluskey
Applying two-pattern tests using scan-mapping. VTS (1996)
Jonathan T.-Y. Chang, Edward J. McCluskey
Detecting Delay Flaws by Very-Low-Voltage Testing. ITC (1996)
Nirmal R. Saxena, Edward J. McCluskey
Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers 45 (11) (1996)
Nur A. Touba, Edward J. McCluskey
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC (1996)
Robert B. Norwood, Edward J. McCluskey
Orthogonal Scan: Low-Overhead Scan for Data Paths. ITC (1996)
Nur A. Touba, Edward J. McCluskey
Test point insertion based on path tracing. VTS (1996)
Robert B. Norwood, Edward J. McCluskey
Synthesis-for-scan and scan chain ordering. VTS (1996)
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell
Analysis and Detection of Timing Failures in an Experimental Test Chip. ITC (1996)
Siyad C. Ma, Edward J. McCluskey
Open faults in BiCMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Nur A. Touba, Edward J. McCluskey
Transformed pseudo-random patterns for BIST. VTS (1995)
Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao
An apparatus for pseudo-deterministic testing. VTS (1995)
Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. ITC (1995)

Edward J. McCluskey.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Edward J. McCluskey