Michel Renovell

ORCID

Publication Activity (10 Years)

Years Active: 1985-2023
Publications (10 Years): 18

Top Venues

Publications

Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS (2023)
Freddy Forero, Víctor H. Champac, Michel Renovell
B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. 19 (1) (2023)
Freddy Forero, Michel Renovell, Víctor H. Champac
B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS (2019)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS (2019)
Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac
Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. 35 (1) (2019)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS (2018)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34 (2) (2018)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI (2017)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS (2017)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. 33 (4) (2017)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Analysis of short defects in FinFET based logic cells. LATS (2017)
Michel Renovell
Spot defect modeling: Past and evolution. DTIS (2017)
Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
Mitigating read & write errors in STT-MRAM memories under DVS. ETS (2017)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS (2016)
Jesus Moreno, Michel Renovell, Víctor H. Champac
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac
Behavior and test of open-gate defects in FinFET based cells. ETS (2016)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI (2016)
Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. ISVLSI (2015)
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
Power-aware voltage tuning for STT-MRAM reliability. ETS (2015)
Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. ISVLSI (2015)
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE (2015)
Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Microelectron. J. 46 (11) (2015)
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
New implementions of predictive alternate analog/RF test with augmented model redundancy. DATE (2014)
Ioannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale
DTIS 2014 foreword. DTIS (2014)
Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell
Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. LATW (2014)
Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos
Solutions for the self-adaptation of communicating systems in operation. IOLTS (2014)
Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
Sram cell stability metric under transient voltage noise. Microelectron. J. 45 (10) (2014)
Serge Bernard, Patrick Garda, Michel Renovell
Editorial. Microelectron. J. 45 (10) (2014)
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements. Microelectron. J. 45 (3) (2014)
Jean Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell
Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. 56 (4) (2014)
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell
Implementing model redundancy in predictive alternate test to improve test confidence. ETS (2013)
Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzerho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti
Accurate and efficient analytical electrical model of antenna for NFC applications. NEWCAS (2013)
Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. 44 (9) (2013)
Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. LATW (2013)
Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. Asian Test Symposium (2013)
Jesus Moreno, Víctor H. Champac, Michel Renovell
Low voltage testing for interconnect opens under process variations. LATW (2012)
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell
Making predictive analog/RF alternate test strategy independent of training set size. ITC (2012)
Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma
Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS (2012)
Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell
Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS (2011)
Jesus Moreno, Víctor H. Champac, Michel Renovell
A new methodology for realistic open defect detection probability evaluation under process variations. VTS (2011)
Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium (2011)
Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. J. Electron. Test. 27 (3) (2011)
Sandra Irobi, Zaid Al-Ars, Michel Renovell
Parasitic memory effect in CMOS SRAMs. IDT (2010)
Mohamed Masmoudi, Michel Renovell
Editorial. Microelectron. J. 41 (8) (2010)
Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS (2009)
Florence Azaïs, Yves Bertrand, Michel Renovell
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS (2009)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
A multi-converter DFT technique for complex SIP: Concepts and validation. ECCTD (2009)
M. Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell
Functional Testing of Processor Cores in FPGA-Based Applications. Comput. Informatics 28 (1) (2009)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design 2008 (2008)
Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. ETS (2008)
Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (2) (2008)
Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS (2008)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. IET Comput. Digit. Tech. 1 (3) (2007)
Florence Azaïs, Laurent Larguier, Michel Renovell
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits. ATS (2007)
Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI (2007)
Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electron. Test. 23 (6) (2007)
Philippe Cauvet, Serge Bernard, Michel Renovell
System-in-Package, a Combination of Challenges and Solutions. ETS (2007)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS (2007)
Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. ATS (2007)
Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA (2006)
Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
Functional Test of Field Programmable Analog Arrays. VTS (2006)
Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency. ATS (2006)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS (2006)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. 22 (2) (2006)
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Des. Test Comput. 23 (3) (2006)
Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
Delta-IDDQ Testing of Resistive Short Defects. ATS (2006)
Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electron. Test. 22 (1) (2006)
Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. 21 (3) (2005)
Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
Built-in self-test of global interconnects of field programmable analog arrays. Microelectron. J. 36 (12) (2005)
Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS (2005)
Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electron. Test. 21 (1) (2005)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. 21 (1) (2005)
Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20 (2) (2005)
Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS (2005)
Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electron. Test. 21 (1) (2005)
Adoración Rueda, Michel Renovell, José Luis Huertas
Guest Editorial. J. Electron. Test. 21 (3) (2005)
Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electron. Test. 21 (2) (2005)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS (2004)
Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS (2004)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA (2004)
Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. 20 (3) (2004)
Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium (2004)
Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. 20 (4) (2004)
Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Automatic test pattern generation for resistive bridging faults. ETS (2004)
Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS (2004)
Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS (2004)
David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
Scan Design and Secure Chip. IOLTS (2004)
Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC (2004)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS (2004)
Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell
A New FPGA for DSP Applications Integrating BIST Capabilities. J. Electron. Test. 20 (4) (2004)
Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
Simulating Resistive Bridging and Stuck-At Faults. ITC (2003)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW (2003)
Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
A New Methodology For ADC Test Flow Optimization. ITC (2003)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS (2003)
Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. 19 (4) (2003)
Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
Modeling feedback bridging faults with non-zero resistance. ETW (2003)
Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell
Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Des. Test Comput. 20 (2) (2003)

Michel Renovell.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Michel Renovell