Satoshi Ohtake

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 14

Top Topics

Monitoring System

Hough Transform

Wireless Sensor

Diagnostic Imaging

Top Venues

Publications

Funakoshi Miyabi, Satoshi Ohtake
Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds. ICCE-Taiwan (2023)
Shunsuke Mukai, Satoshi Ohtake
Vibration Measurement Experiment of Rails at Shinkansen Rail Yard in Kumamoto. GCCE (2023)
Toshiyuki Haramaki, Satoshi Ohtake
A Method of Controlling Devices Remotely in Online Embedded System Engineer Training. ICCE-Taiwan (2023)
Shunsuke Mukai, Satoshi Ohtake
Field Monitoring System for Frost Damage Warning and Quality Difference Analysis of Tea Leaves. ICCE-Taiwan (2023)
Tsuneo Kagawa, Masaya Ikemoto, Satoshi Ohtake
A robust method of IC seating inspection in burn-in sockets using Hough transform. ICCE-TW (2022)
Yuki Echigo, Satoshi Ohtake
Vibration Measurement of Signal Bonds for Shinkansen. ICCE (2021)
Kotaro Iwamoto, Satoshi Ohtake
A Warning System with Multiple Sensors for Avoiding Collision of Bicycles. ICCE-TW (2020)
Yui Uehara, Satoshi Ohtake
Temperature Monitoring in Shinkansen Signal and Communication House. ICCE (2020)
Yui Uehara, Satoshi Ohtake
Factory Environment Monitoring: A Japanese Tea Manufacturer's Case. ICCE (2019)
Yui Uehara, Satoshi Ohtake, Takamoto Fukura
Monitoring Sake Brewing Processes with Compact Wireless Sensors. ICCE-Berlin (2019)
Yui Uehara, Satoshi Ohtake, Takayuki Karyu
A Koji Temperature Monitoring System. ICCE-TW (2019)
Yushiro Hiramoto, Satoshi Ohtake, Hiroshi Takahashi
A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures. ATS (2019)
Yushiro Hiramoto, Satoshi Ohtake
A Method of Hardware-Trojan Detection Using Design Verification Techniques. CISIS (2018)
Satoshi Ohtake, Daichi Shimazu
An approach to LFSR-based X-masking for built-in self-test. LATS (2017)
Renji Ono, Satoshi Ohtake
A Method of Diagnostic Test Generation for Transition Faults. PRDC (2015)
Kosuke Sawaki, Satoshi Ohtake
A method of LFSR seed generation for hierarchical BIST. IDT (2015)
Shuichi Sato, Satoshi Ohtake
A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model. DDECS (2015)
Takanori Moriyasu, Satoshi Ohtake
A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults. LATS (2015)
Takanori Moriyasu, Satoshi Ohtake
A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG. CISIS (2013)
Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
F-Scan: A DFT Method for Functional Scan at RTL. IEICE Trans. Inf. Syst. (1) (2011)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. ETS (2011)
Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. 6 (4) (2011)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA (2010)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
Constrained ATPG for functional RTL circuits using F-Scan. ITC (2010)
Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
A synthesis method to propagate false path information from RTL to gate level. DDECS (2010)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. (7) (2010)
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium (2010)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS (2009)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC (2009)
Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Trans. Inf. Syst. (3) (2008)
Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS (2008)
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. (1) (2007)
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD (2007)
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS (2007)
Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT (2006)
Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA (2006)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC (2006)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) (2006)
Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Design for Testability of Software-Based Self-Test for Processors. ATS (2006)
Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium (2005)
Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium (2005)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. ETS (2005)
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. 20 (3) (2004)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
A design methodology to realize delay testable controllers using state transition information. ETS (2004)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium (2003)
Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. DATE (2003)
Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. VTS (2002)
Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara
Design for Two-Pattern Testability of Controller-Data Path Circuits. Asian Test Symposium (2002)
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
A nonscan DFT method for controllers to provide complete fault efficiency. Systems and Computers in Japan 33 (5) (2002)
Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
Design for Hierarchical Two-Pattern Testability of Data Paths. Asian Test Symposium (2001)
Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. ASP-DAC (2001)
Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design (2001)
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. J. Electron. Test. 16 (5) (2000)
Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
A non-scan DFT method at register-transfer level to achieve complete fault efficiency. ASP-DAC (2000)
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium (1999)
Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium (1999)
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. Asian Test Symposium (1998)
Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki
A sequential circuit structure with combinational test generation complexity and its application. Systems and Computers in Japan 28 (11) (1997)
Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
Sequential Test Generation Based on Circuit Pseudo-Transformation. Asian Test Symposium (1997)