Mineo Kaneko

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 36

Top Topics

High Level Synthesis

Renewable Energy

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ACM Great Lakes Symposium on VLSI

Publications

Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
Design Automation for Charge Recovery Logic. ISCAS (2024)
Saher Javaid, Mineo Kaneko, Yasuo Tan
Energy Balancing of Power System Considering Periodic Behavioral Pattern of Renewable Energy Sources and Demands. IEEE Access 12 (2024)
Yuya Ushioda, Mineo Kaneko
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko
Optimal Location and Sizing of Renewable Distributed Generators for Improving Robust Voltage Stability Against Uncontrollable Reactive Compensation. IEEE Access 11 (2023)
Mineo Kaneko
Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders. ISCAS (2023)
Saher Javaid, Mineo Kaneko, Yasuo Tan
Supply-Dominated Energy Balancing for Periodic Operation of Power System. ICCE-Taiwan (2023)
Saher Javaid, Mineo Kaneko, Yasuo Tan, Nouman Ashraf
LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation. ICCE-TW (2022)
Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko
Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration. ISCAS (2022)
Yuya Ushioda, Mineo Kaneko
Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem. ICCD (2022)
Saher Javaid, Mineo Kaneko, Yasuo Tan
Storage Minimization Considering System Conditions of Power Flow System. ICCE-TW (2021)
Mineo Kaneko
Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization. ISCAS (2021)
Mineo Kaneko
Two-Graph Approach to Temperature Dependent Skew Scheduling. ISQED (2020)
Masato Tatsuoka, Mineo Kaneko
High Level Congestion Detection from C/C++ Source Code for High Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2020)
Mineo Kaneko
Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders. ISCAS (2020)
Saher Javaid, Mineo Kaneko, Yasuo Tan
System Condition for Controllable Power Flow System Considering Reaction Delay. ICCE-TW (2020)
Mineo Kaneko
A Novel Framework for Procedural Construction of Parallel Prefix Adders. ISCAS (2019)
Saher Javaid, Mineo Kaneko, Yasuo Tan
A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices. GCCE (2019)
Saher Javaid, Mineo Kaneko, Yasuo Tan
Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty. ICCE-TW (2019)
Mineo Kaneko
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Masato Tatsuoka, Mineo Kaneko
Wire congestion aware high level synthesis flow with source code compiler. ICICDT (2018)
Takayuki Moto, Mineo Kaneko
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing. ISCAS (2018)
Mineo Kaneko
KKT-condition inspired solution of DVFS with limited number of voltage levels. ISCAS (2017)
Renyuan Zhang, Mineo Kaneko
A random access analog memory with master-slave structure for implementing hexadecimal logic. SoCC (2017)
Junghoon Oh, Mineo Kaneko
Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Mineo Kaneko
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Mineo Kaneko
Margin aware timing test and tuning algorithm for post-silicon skew tuning. MWSCAS (2017)
Junghoon Oh, Mineo Kaneko
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components. ISVLSI (2016)
Junghoon Oh, Mineo Kaneko
Mixed error correction scheme and its design optimization for soft-error tolerant datapaths. APCCAS (2016)
Renyuan Zhang, Mineo Kaneko
A 16-valued logic FPGA architecture employing analog memory circuit. ISCAS (2016)
Mineo Kaneko
KKT-condition based study on DVFS for heterogeneous task set. APCCAS (2016)
Junghoon Oh, Mineo Kaneko
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Mineo Kaneko
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling. ACM Great Lakes Symposium on VLSI (2015)
Renyuan Zhang, Mineo Kaneko
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Junghoon Oh, Mineo Kaneko
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis. ISCAS (2015)
Renyuan Zhang, Mineo Kaneko
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism. ISCAS (2015)
Keisuke Inoue, Mineo Kaneko
Bitwidth-aware register allocation and binding for clock period minimization. MWSCAS (2015)
Renyuan Zhang, Mineo Kaneko
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism. ACM Great Lakes Symposium on VLSI (2014)
Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim
Priority based maximum consuming power control in smart homes. ISGT (2014)
Mineo Kaneko
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]. ACM Great Lakes Symposium on VLSI (2014)
Mineo Kaneko, Yutaka Tsuboishi
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis. ISCAS (2014)
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops (2014)
Keisuke Inoue, Mineo Kaneko
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Keisuke Inoue, Mineo Kaneko
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2013)
Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu
An efficient approach for designing and minimizing reversible programmable logic arrays. ACM Great Lakes Symposium on VLSI (2012)
Mineo Kaneko
Timing-test scheduling for constraint-graph based post-silicon skew tuning. ICCD (2012)
Keisuke Inoue, Mineo Kaneko
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. MWSCAS (2012)
Keisuke Inoue, Mineo Kaneko
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. ISQED (2012)
Keisuke Inoue, Mineo Kaneko
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Mineo Kaneko, Jian Li
Post-silicon skew tuning algorithm utilizing setup and hold timing tests. ISCAS (2012)
Keisuke Inoue, Mineo Kaneko
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. ACM Great Lakes Symposium on VLSI (2012)
Keisuke Inoue, Mineo Kaneko
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. ASP-DAC (2012)
Keisuke Inoue, Mineo Kaneko
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. ISCAS (2012)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2011)
Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Mineo Kaneko
A complete framework of simultaneous functional unit and register binding with skew scheduling. ISQED (2011)
Keisuke Inoue, Mineo Kaneko
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC (2011)
Keisuke Inoue, Mineo Kaneko
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. Inf. Media Technol. 6 (4) (2011)
Mineo Kaneko, Keisuke Inoue
Ordered coloring-based resource binding for datapaths with improved skew-adjustability. ACM Great Lakes Symposium on VLSI (2011)
Keisuke Inoue, Mineo Kaneko
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ISCAS (2011)
Keisuke Inoue, Mineo Kaneko
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Tsuyoshi Iwagaki, Mineo Kaneko
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties. DELTA (2010)
Keisuke Inoue, Mineo Kaneko
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI (2010)
Keisuke Inoue, Mineo Kaneko
Optimal register assignment with minimum-delay compensation for latch-based design. APCCAS (2010)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI (2009)
Tsuyoshi Iwagaki, Mineo Kaneko
On the derivation of a minimum test set in high quality transition testing. LATW (2009)
Takayuki Obata, Mineo Kaneko
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis. ISCAS (2009)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Safe clocking register assignment in datapath synthesis. ICCD (2008)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Takayuki Obata, Mineo Kaneko
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Takayuki Obata, Mineo Kaneko
Concurrent skew and control step assignments in RT-level datapath synthesis. ISCAS (2008)
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD (2007)
Koji Ohashi, Mineo Kaneko
Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2007)
Koji Ohashi, Mineo Kaneko
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ACM Great Lakes Symposium on VLSI (2007)
Mineo Kaneko
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. APCCAS (2006)
Koji Ohashi, Mineo Kaneko
Statistical schedule length analysis in asynchronous datapath synthesis. ISCAS (1) (2005)
Koji Ohashi, Mineo Kaneko
Statistical Analysis Driven Synthesis of Asynchronous Systems. ICCD (2005)
Mineo Kaneko, Kazuaki Oshio
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. ISCAS (5) (2003)
Satoshi Tayu, Mineo Kaneko
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko
Two-dimensional placement method based on divide-and-replacement. APCCAS (2) (2002)
Mineo Kaneko, Jun'ichi Yokoyama, Satoshi Tayu
3D scheduling based on code space exploration for dynamically reconfigurable systems. ISCAS (5) (2002)
Koji Ohashi, Mineo Kaneko
Heuristic assignment-driven scheduling for data-path synthesis. ISCAS (4) (2002)
Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko
Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Satoshi Tayu, Mineo Kaneko
Characterization and computation of Steiner wiring based on Elmore's delay model. APCCAS (2) (2002)
Mineo Kaneko, Yasuaki Maekawa
Extended dimensional threshold filtering-a bridge between FIR filter and median type filter. ISCAS (2) (2001)
Choon-Sik Park, Mineo Kaneko
An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter. ISCAS (2000)
Koji Ohashi, Mineo Kaneko, Satoshi Tayu
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. ICCD (2000)
Mineo Kaneko, Yoshitaka Nishio, Satoshi Tayu
Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications. ISCAS (2000)
Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. ISPAN (2000)
Mineo Kaneko
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power. ISCAS (1) (1999)
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (1) (1998)
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
VLSI/PCB placement with obstacles based on sequence-pair. ISPD (1997)
Fernando Gil Vianna Resende Jr., Paulo S. R. Diniz, Mineo Kaneko, Akinori Nishihara
Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors. ICASSP (1997)
Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko
AR Spectrum Estimation Based on Wavelet Representation. ISCAS (1994)
Mineo Kaneko, Kazuhiro Sakaguchi
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. ISCAS (1994)
Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. ISCAS (1994)
Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi
A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. ISCAS (1993)