Hafiz Md. Hasan Babu

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 20

Top Topics

Logic Synthesis

Top Venues

Publications

Abdus Sattar, Md. Asif Mahmud Ridoy, Aloke Kumar Saha, Hafiz Md. Hasan Babu, Mohammad Nurul Huda
A comprehensive approach to detecting chemical adulteration in fruits using computer vision, deep learning, and chemical sensors. Intell. Syst. Appl. 23 (2024)
Amanul Islam, Fazidah Othman, Nazmus Sakib, Hafiz Md. Hasan Babu
Prevention of shoulder-surfing attacks using shifting condition using digraph substitution rules. CoRR (2023)
Hafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Tamanna Tabassum, Mohammed Nasir Uddin
DNA Technology for Multi-Valued Data Storage using Read Only Memory. FLAP 9 (3) (2022)
Samrat Kumar Dey, Khandaker Mohammad Mohi Uddin, Hafiz Md. Hasan Babu, Md. Mahbubur Rahman, Arpita Howlader, K. M. Aslam Uddin
-MI: A hybrid feature selection based machine learning approach in diagnosis of chronic kidney disease. Intell. Syst. Appl. 16 (2022)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design. CoRR (2022)
Md. Mahbubur Rahman, Md. Saikat Islam Khan, Hafiz Md. Hasan Babu
BreastMultiNet: A multi-scale feature fusion method using deep neural network to detect breast cancer. Array 16 (2022)
Hafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Rownak Borhan Himel, Nitish Biswas
Quantum Technology for Comparator Circuit. ISQED (2022)
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
A Fast FPGA-Based BCD Adder. Circuits Syst. Signal Process. 37 (10) (2018)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. ISVLSI (2017)
Hafiz Md. Hasan Babu, Lafifa Jamal, Sayanton Vhaduri Dibbo, Ashis Kumer Biswas
Area and Delay Efficient Design of a Quantum Bit String Comparator. ISVLSI (2017)
Hafiz Md. Hasan Babu
Cost-efficient design of a quantum multiplier-accumulator unit. Quantum Inf. Process. 16 (1) (2017)
Hafiz Md. Hasan Babu, Md. Solaiman Mia, Ashis Kumer Biswas
Efficient Techniques for Fault Detection and Correction of Reversible Circuits. J. Electron. Test. 33 (5) (2017)
Nazma Tara, Hafiz Md. Hasan Babu, Lafifa Jamal
Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array. Sustain. Comput. Informatics Syst. 16 (2017)
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. IET Circuits Devices Syst. 10 (3) (2016)
Sadia Nowrin, Lafifa Jamal, Hafiz Md. Hasan Babu
Design of an optimized reversible bidirectional barrel shifter. ISCAS (2016)
Sayanton Vhaduri Dibbo, Hafiz Md. Hasan Babu, Lafifa Jamal
An efficient design technique of a quantum divider circuit. ISCAS (2016)
Hafiz Md. Hasan Babu, Md. Solaiman Mia
Design of a compact reversible fault tolerant division circuit. Microelectron. J. 51 (2016)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu
A LUT-based matrix multiplication using neural networks. ISCAS (2016)
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. VLSI Design (2016)
Nazma Tara, Hafiz Md. Hasan Babu, Nawshi Matin
Logic Synthesis in Reversible PLA. VLSI Design (2016)
Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. VLSI Design (2015)
Md. Shamsujjoha, Sirin Nahar Sathi, Golam Sorwar, Fahmida Hossain, Md. Nawab Yousuf Ali, Hafiz Md. Hasan Babu
An Efficient Design of a Reversible Fault Tolerant n -to-2 ^n Sequence Counter Using Nano Meter MOS Transistors. ICSI (3) (2015)
Lafifa Jamal, Hafiz Md. Hasan Babu
Design and Implementation of a Reversible Central Processing Unit. ISVLSI (2015)
Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
A compact representation of a quantum controlled ternary barrel shifter. ISCAS (2015)
Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing. ISMVL (2015)
Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
A compact realization of an n-bit quantum carry skip adder circuit with optimal delay. AHS (2014)
Nusrat Jahan Lisa, Hafiz Md. Hasan Babu
-to-n BCD priority encoder. NANOARCH (2014)
Md. Mostafizur Rahman, Atsuhiro Takasu, Hafiz Md. Hasan Babu
A Cascading Wavelet-Feed Forward Neural Network Approach for Forecasting Traffic Flow. EDBT/ICDT Workshops (2014)
Ankur Sarker, Hafiz Md. Hasan Babu, Md. Saiful Islam
A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid. ISCAS (2014)
Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar, Tsutomu Sasao
Approach to design a compact reversible low power binary comparator. IET Comput. Digit. Tech. 8 (3) (2014)
Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal
Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis. Microelectron. J. 44 (6) (2013)
Tanvir Ahmed, Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid, Md. Atiqur Rahman, Hafiz Md. Hasan Babu
A novel approach to design a reversible shifter circuit using DNA. SoCC (2013)
Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid, Hafiz Md. Hasan Babu
Implementation of reversible multiplier circuit using Deoxyribonucleic acid. BIBE (2013)
Lafifa Jamal, Md. Masbaul Alam, Hafiz Md. Hasan Babu
An efficient approach to design a reversible control unit of a processor. Sustain. Comput. Informatics Syst. 3 (4) (2013)
Hafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. SoCC (2013)
Lafifa Jamal, Md. Mushfiqur Rahman, Hafiz Md. Hasan Babu
An optimal design of a fault tolerant reversible multiplier. SoCC (2013)
Md. Shamsujjoha, Hafiz Md. Hasan Babu
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. VLSI Design (2013)
Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury
Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. VLSI Design (2013)
Lafifa Jamal, Hafiz Md. Hasan Babu
Efficient approaches to design a reversible floating point divider. ISCAS (2013)
Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu
An efficient approach for designing and minimizing reversible programmable logic arrays. ACM Great Lakes Symposium on VLSI (2012)
Lafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu
On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. VDAT (2012)
Ankur Sarker, Tanvir Ahmed, S. M. Mahbubur Rashid, Shahed Anwar, Lafifa Jamal, Nazma Tara, Md. Masbaul Alam, Hafiz Md. Hasan Babu
Realization of Reversible Logic in DNA Computing. BIBE (2011)
Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu
Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing CoRR (2010)
Hafiz Md. Hasan Babu, Md. Saiful Islam, Md. Rafiqul Islam, Lafifa Jamal, Abu Ahmed Ferdaus, Muhammad Rezaul Karim, Abdullah Al Mahmud
Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings CoRR (2010)
Md. Rafiqul Islam, Md. Saiful Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Hafiz Md. Hasan Babu
Variable Block Carry Skip Logic using Reversible Gates CoRR (2010)
Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu
Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles CoRR (2010)
Irina Hashmi, Hafiz Md. Hasan Babu
An Efficient Design of a Reversible Barrel Shifter. VLSI Design (2010)
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam
Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing CoRR (2010)
Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. VLSI Design (2008)
Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. DFT (2008)
Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu
Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectron. J. 39 (12) (2008)
Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. VLSI Design (2006)
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
Design of a compact reversible binary coded decimal adder circuit. J. Syst. Archit. 52 (5) (2006)
Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES (2006)
Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. DSD (2005)
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design (2005)
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury
A heuristic approach to synthesize Boolean functions using TANT network. ISCAS (2) (2004)
Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman
On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. ISMVL (2004)
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury
Synthesis of Full-Adder Circuit Using Reversible Logic. VLSI Design (2004)
Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. DSD (2004)
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury
Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD (2003)
Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar
A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. Asian Test Symposium (2003)
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. ISMVL (2003)
Hafiz Md. Hasan Babu, Tsutomu Sasao
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL (2000)
Hafiz Md. Hasan Babu, Tsutomu Sasao
Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL (1999)
Hafiz Md. Hasan Babu, Tsutomu Sasao
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL (1998)