Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.
Zarrin Tasnim SwornaMubin Ul HaqueNazma TaraHafiz Md. Hasan BabuAshis Kumer BiswasPublished in: IET Circuits Devices Syst. (2016)
Keyphrases
- low power
- low power consumption
- logic circuits
- low cost
- digital signal processing
- power consumption
- power dissipation
- single chip
- high speed
- field programmable gate array
- vlsi architecture
- real time
- hardware implementation
- cmos technology
- gate array
- fine grained
- power reduction
- fpga device
- data flow
- embedded systems
- hardware architecture
- nm technology
- programmable logic
- circuit design
- ultra low power
- storage devices
- parallel machines
- source code
- image processing
- information systems