Zarrin Tasnim Sworna

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 13

Top Topics

Application Programming Interfaces

Intrusion Detection

Matrix Multiplication

Top Venues

ACM Trans. Softw. Eng. Methodol.

Publications

Zarrin Tasnim Sworna, Anjitha Sreekumar, Chadni Islam, Muhammad Ali Babar
Security Tools' API Recommendation Using Machine Learning. ENASE (2023)
Zarrin Tasnim Sworna, Zahra Mousavi, Muhammad Ali Babar
NLP methods in host-based intrusion detection systems: A systematic review and future directions. J. Netw. Comput. Appl. 220 (2023)
Zarrin Tasnim Sworna, Chadni Islam, Muhammad Ali Babar
APIRO: A Framework for Automated Security Tools API Recommendation. ACM Trans. Softw. Eng. Methodol. 32 (1) (2023)
Zarrin Tasnim Sworna, Muhammad Ali Babar, Anjitha Sreekumar
IRP2API: Automated Mapping of Cyber Security Incident Response Plan to Security Tools' APIs. SANER (2023)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design. CoRR (2022)
Mubin Ul Haque, Isuru Dharmadasa, Zarrin Tasnim Sworna, Roshan Namal Rajapakse, Hussain Ahmad
"I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data. CoRR (2022)
Zarrin Tasnim Sworna, Zahra Mousavi, Muhammad Ali Babar
NLP Methods in Host-based Intrusion Detection Systems: A Systematic Review and Future Directions. CoRR (2022)
Zarrin Tasnim Sworna, Chadni Islam, Muhammad Ali Babar
APIRO: A Framework for Automated Security Tools API Recommendation. CoRR (2022)
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
A Fast FPGA-Based BCD Adder. Circuits Syst. Signal Process. 37 (10) (2018)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. ISVLSI (2017)
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. IET Circuits Devices Syst. 10 (3) (2016)
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu
A LUT-based matrix multiplication using neural networks. ISCAS (2016)
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. VLSI Design (2016)