A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors.
Md. ShamsujjohaHafiz Md. Hasan BabuPublished in: VLSI Design (2013)
Keyphrases
- fault tolerant
- low power
- fault tolerance
- power consumption
- low cost
- high speed
- distributed systems
- single chip
- error concealment
- vlsi circuits
- low density parity check
- logic circuits
- load balancing
- vlsi architecture
- error detection
- video codec
- low complexity
- gate array
- cmos technology
- error resilient
- power reduction
- mixed signal
- rate allocation
- distributed video coding