Keisuke Inoue

Publication Activity (10 Years)

Years Active: 1991-2020
Publications (10 Years): 6

Top Topics

Optimization Method

Extended Abstract

Nelder Mead Simplex

Top Venues

Publications

Keisuke Inoue, Fumihiko Sakaue, Jun Sato
Removing Reflection from In-vehicle Camera Image. VISIGRAPP (4: VISAPP) (2020)
Keisuke Inoue
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. VLSI-SoC (2019)
Keisuke Inoue, Toshiki Honda, Kohei Mukaiyama, Tetsushi Ohki, Masakatsu Nishigaki
Automatic Examination-Based Whitelist Generation for XSS Attack Detection. BWCCA (2018)
Keisuke Inoue
A dependable ASIC architecture with RT-level rollback for controller soft error recovery. NORCAS (2017)
Keisuke Inoue
ECC module optimization for storage transient error-tolerant ASICs. ICECS (2016)
Keisuke Inoue, Mineo Kaneko
Bitwidth-aware register allocation and binding for clock period minimization. MWSCAS (2015)
Keisuke Inoue, Takao Nishizeki
Spanning Distribution Forests of Graphs - (Extended Abstract). FAW (2014)
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops (2014)
Keisuke Inoue, Mineo Kaneko
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Keisuke Inoue, Mineo Kaneko
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2013)
Keisuke Inoue, Mineo Kaneko
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. MWSCAS (2012)
Keisuke Inoue, Mineo Kaneko
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. ISQED (2012)
Keisuke Inoue, Mineo Kaneko
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Keisuke Inoue, Mineo Kaneko
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. ACM Great Lakes Symposium on VLSI (2012)
Keisuke Inoue, Mineo Kaneko
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. ASP-DAC (2012)
Keisuke Inoue, Mineo Kaneko
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. ISCAS (2012)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2011)
Keisuke Inoue, Mineo Kaneko
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC (2011)
Keisuke Inoue, Mineo Kaneko
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. Inf. Media Technol. 6 (4) (2011)
Mineo Kaneko, Keisuke Inoue
Ordered coloring-based resource binding for datapaths with improved skew-adjustability. ACM Great Lakes Symposium on VLSI (2011)
Keisuke Inoue, Mineo Kaneko
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ISCAS (2011)
Keisuke Inoue, Mineo Kaneko
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Keisuke Inoue, Mineo Kaneko
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI (2010)
Keisuke Inoue, Mineo Kaneko
Optimal register assignment with minimum-delay compensation for latch-based design. APCCAS (2010)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI (2009)
Keisuke Inoue
Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues. ASIST (2009)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Safe clocking register assignment in datapath synthesis. ICCD (2008)
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
James Howison, Keisuke Inoue, Kevin Crowston
Social dynamics of free and open source team communications. OSS (2006)
Tsuyoshi Idé, Keisuke Inoue
Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations. SDM (2005)
Kazuhiro Shimonomura, Keisuke Inoue, Seiji Kameda, Tetsuya Yagi
A Novel Robot Vision Applicable to Real-time Target Tracking. J. Robotics Mechatronics 15 (2) (2003)
Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata
A 250-MHz single-chip multiprocessor for audio and video signal processing. IEEE J. Solid State Circuits 36 (11) (2001)
Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada
Face clustering of a large-scale CAD model for surface mesh generation. Comput. Aided Des. 33 (3) (2001)
Atsushi Yamada, Keisuke Inoue, Takayuki Itoh, Kenji Shimada
An Approach for Generating Meshes Similar to A Reference Mesh. IMR (2000)
Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano
ISIS: Multiprocessor Simulator Library. Applied Informatics (1999)
Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada
Clustering Large Number of Faces for 2-Dimensional Mesh Generation. IMR (1999)
Takayuki Itoh, Kenji Shimada, Keisuke Inoue, Atsushi Yamada, Tomotake Furuhata
Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control. IMR (1998)
Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par (1997)
Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano
A study on snoop cache systems for single-chip multiprocessors. Systems and Computers in Japan 28 (2) (1997)
Toru Ohira, Keisuke Inoue, Yoshiteru Takeshima
Traffic Control Model with Neural Network Analogy. ICONIP (2) (1997)
Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL (1996)
Shuichi Shimizu, Keisuke Inoue, Masayuki Numao
An ATMS-based geometric constraint solver for 3D CAD. ICTAI (1991)