Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis.
Keisuke InoueMineo KanekoPublished in: ISCAS (2012)
Keyphrases
- low power
- high speed
- power consumption
- high level synthesis
- low cost
- power dissipation
- cmos technology
- single chip
- vlsi architecture
- vlsi circuits
- low power consumption
- real time
- high power
- logic circuits
- wireless transmission
- power reduction
- energy efficiency
- digital signal processing
- delay insensitive
- image sensor
- mixed signal
- embedded systems
- gate array
- ultra low power