Shin'ichi Wakabayashi

Publication Activity (10 Years)

Years Active: 1985-2023
Publications (10 Years): 10

Top Topics

Approximate Nearest Neighbor

Concurrency Control

Feature Vectors

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Inf. Media Technol.

Publications

Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. 16 (2023)
Chuki Hayama, Yoko Kamidoi, Shin'ichi Wakabayashi
Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet. COMPSAC (2022)
Yoko Kamidoi, Ryousuke Yamauchi, Shin'ichi Wakabayashi
A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's Implementation. IEEE Access 9 (2021)
Shun Kawamoto, Yoko Kamidoi, Shin'ichi Wakabayashi
A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds. COMPSAC (2020)
Takumi Makino, Yoko Kamidoi, Shin'ichi Wakabayashi
A Verifiable Secret Sharing Scheme without Using Multi-Party Computations. COMPSAC (2020)
Ryosuke Yamauchi, Yoko Kamidoi, Shin'ichi Wakabayashi
A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain. COMPSAC (1) (2019)
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. DSD (2018)
Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. DEXA (2) (2018)
Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
A Nearest Neighbor Search Engine Using Distance-Based Hashing. FPT (2018)
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. FPT (2016)
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Inf. Media Technol. 9 (4) (2014)
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops (2014)
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. DSD (2013)
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. DSD (2013)
Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL (2011)
Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. DSD (2011)
Yuichiro Utan, Shin'ichi Wakabayashi, Shinobu Nagayama
An FPGA-based text search engine for approximate regular expression matching. FPT (2010)
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama
A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. ERSA (2009)
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama
A systolic regular expression pattern matching engine and its application to network intrusion detection. FPT (2008)
Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama
A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. FPT (2007)
Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. PDPTA (2007)
Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A Decision Method of Attribute Importance for Classification by Outlier Detection. ICDE Workshops (2006)
Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama
FPGA implementation of tabu search for the quadratic assignment problem. FPT (2006)
Takeshi Fushimi, Yoko Kamidoi, Shin'ichi Wakabayashi
An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. ICDE Workshops (2005)
Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
Feature Extraction of Clusters Based on FlexDice. ICDE Workshops (2005)
Shin'ichi Wakabayashi, Kenji Kikuchi
Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. FPT (2005)
Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A Clustering Method Using an Irregular Size Cell Graph. RIDE (2005)
Shin'ichi Wakabayashi, Kenji Kikuchi
An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. FPL (2004)
Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem. Algorithmica 32 (2) (2002)
Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33 (12) (2002)
Shin'ichi Wakabayashi, Nobuyuki Iwauchi, Hajime Kubota
A hierarchical standard cell placement method based on a new cluster placement model. APCCAS (1) (2002)
Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32 (1) (2001)
Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC (2000)
Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno
Genetic algorithm accelerator GAA-II. ASP-DAC (2000)
Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS (2000)
Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC (1999)
Tetsushi Koide, Shin'ichi Wakabayashi
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. 27 (1) (1999)
Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC (1999)
Tetsushi Koide, Shin'ichi Wakabayashi
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC (1998)
Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN (1998)
Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. 24 (1) (1997)
Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC (1997)
Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A three-layer over-the-cell multi-channel router for a new cell model. Integr. 21 (3) (1996)
Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
An MCM Routing Algorithm Considering Crosstalk. ISCAS (1995)
Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC (1995)
Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS (1995)
Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC (1995)
Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC (1995)
Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A Floorplanning Method with Topological Constraint Manipulation. ISCAS (1994)
Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
On Three-Way Graph Partitioning. ISCAS (1994)
Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS (1994)
Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A new global routing algorithm for over-the-cell routing in standard cell layouts. EURO-DAC (1993)
Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS (1993)
Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
An optimal channel pin assignment with multiple intervals for building block layout. EURO-DAC (1992)
Jun'ichi Miyao, Shin'ichi Wakabayashi, Noriyoshi Yoshida, Yasushi Ohtahara
Visualized and modeless programming environment for form manipulation language. VL (1989)
Shin'ichi Wakabayashi, Tohru Kikuno, Noriyoshi Yoshida
Design of hardware algorithms by recurrence relations. Systems and Computers in Japan 16 (3) (1985)