Baris Taskin

ORCID

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 58

Top Venues

ISCAS

IEEE Trans. Very Large Scale Integr. Syst.

ICCD

ISVLSI

Publications

Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin
High-Speed Phase-Based Computing. ISCAS (2024)
Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
Design Automation for Charge Recovery Logic. ISCAS (2024)
Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. ISCAS (2022)
Amlan Ganguly, Sergi Abadal, Ishan G. Thakkar, Natalie Enright Jerger, Marc D. Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro 42 (3) (2022)
Ragh Kuttappa, Longfei Wang, Selçuk Köse, Baris Taskin
Multiphase Digital Low-Dropout Regulators. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Ragh Kuttappa, Baris Taskin
A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators. ISCAS (2022)
Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin
Scalable Resonant Power Clock Generation for Adiabatic Logic Design. ISVLSI (2021)
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (4) (2021)
Ragh Kuttappa, Baris Taskin
FinFET - Based Low Swing Rotary Traveling Wave Oscillators. ISCAS (2020)
Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead
SnackNoC: Processing in the Communication Layer. HPCA (2020)
Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. ISCAS (2020)
Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, Baris Taskin
TSV Antennas for Multi-Band Wireless Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (1) (2020)
Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin
Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS (2019)
Baris Taskin
On-chip wireless interconnect paradigm. NoCArc@MICRO (2019)
Ragh Kuttappa, Selçuk Köse, Baris Taskin
FOPAC: Flexible On-Chip Power and Clock. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2019)
Scott Lerner, Baris Taskin
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Longfei Wang, Ragh Kuttappa, Baris Taskin, Selçuk Köse
Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation. SLIP (2019)
Scott Lerner, Isikcan Yilmaz, Baris Taskin
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Leo Filippini, Baris Taskin
The Adiabatically Driven StrongARM Comparator. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Vasil Pano, Ragh Kuttappa, Baris Taskin
3D NoCs with active interposer for multi-die systems. NOCS (2019)
Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, Hamid Mahmoodi
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED (2019)
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI (2019)
Ragh Kuttappa, Baris Taskin
Low Frequency Rotary Traveling Wave Oscillators. ISCAS (2018)
Michael Lui, Karthik Sangaiah, Mark Hempstead, Baris Taskin
Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces. ISPASS (2018)
Ankit More, Vasil Pano, Baris Taskin
Vertical Arbitration-Free 3-D NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (9) (2018)
Karthik Sangaiah, Michael Lui, Radhika Jagtap, Stephan Diestelhorst, Siddharth Nilakantan, Ankit More, Baris Taskin, Mark Hempstead
SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads. ACM Trans. Archit. Code Optim. 15 (1) (2018)
Leo Filippini, Baris Taskin
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. ISCAS (2018)
Scott Lerner, Vasil Pano, Baris Taskin
NoC Router Lifetime Improvement using Per-Port Router Utilization. ISCAS (2018)
Scott Lerner, Baris Taskin
Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. IGSC (2018)
Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. ISCAS (2018)
Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin
Reconfigurable threshold logic gates using optoelectronic capacitors. DATE (2017)
Leo Filippini, Diane Lim, Lunal Khuon, Baris Taskin
Wireless charge recovery system for implanted electroencephalography applications in mice. ISQED (2017)
Scott Lerner, Eric Leggett, Baris Taskin
Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP (2017)
Scott Lerner, Baris Taskin
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. ISVLSI (2017)
Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar
Wireless NoCs Using Directional and Substrate Propagation Antennas. ISVLSI (2017)
Leo Filippini, Lunal Khuon, Baris Taskin
Charge recovery implementation of an analog comparator: Initial results. MWSCAS (2017)
Tsung-Yi Ho, Baris Taskin
Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016. Integr. 58 (2017)
Scott Lerner, Baris Taskin
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. ISQED (2017)
Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS (2017)
Leo Filippini, Baris Taskin
A charge recovery logic system bus. SLIP (2017)
Leo Filippini, Baris Taskin
Charge recovery logic for thermal harvesting applications. ISCAS (2016)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Exploiting useful skew in gated low voltage clock trees. ISCAS (2016)
Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar
Wireless Network-on-Chip analysis of propagation technique for on-chip communication. ICCD (2016)
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 24 (10) (2016)
Vasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin
Energy aware routing of multi-level Network-on-Chip traffic. ICCD (2016)
Ying Teng, Baris Taskin
ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Karthik Sangaiah, Mark Hempstead, Baris Taskin
Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling. ICCAD (2015)
Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead
Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation. ISPASS (2015)
Leo Filippini, Emre Salman, Baris Taskin
A wirelessly powered system with charge recovery logic. ICCD (2015)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ACM Great Lakes Symposium on VLSI (2015)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Enhanced level shifter for multi-voltage operation. ISCAS (2015)
Ankit More, Baris Taskin
Locality-Aware Network Utilization Balancing in NoCs. ACM Trans. Design Autom. Electr. Syst. 21 (1) (2015)
Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ACM Great Lakes Symposium on VLSI (2015)
Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping. VLSI Design (2015)
Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin
FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. 12 (2) (2015)
Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. VLSI Design (2015)
Can Sitik, Leo Filippini, Emre Salman, Baris Taskin
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI (2014)
Ying Teng, Baris Taskin
Frequency-centric resonant rotary clock distribution network design. ICCAD (2014)
Julian Kemmerer, Baris Taskin
Range-based dynamic routing of hierarchical on chip network traffic. SLIP (2014)
Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More
Static thread mapping for NoCs via binary instrumentation traces. ICCD (2014)
Can Sitik, Scott Lerner, Baris Taskin
Timing characterization of clock buffers for clock tree synthesis. ICCD (2014)
Can Sitik, Baris Taskin
Iterative skew minimization for low swing clocks. Integr. 47 (3) (2014)
Can Sitik, Baris Taskin
Skew-bounded low swing clock tree optimization. ACM Great Lakes Symposium on VLSI (2013)
Baris Taskin
Wireless on Networks-on-Chip. SLIP (2013)
Ying Teng, Baris Taskin
Sparse-rotary oscillator array (SROA) design for power and skew reduction. DATE (2013)
Can Sitik, Prawat Nagvajara, Baris Taskin
A microcontroller-based embedded system design course with PSoC3. MSE (2013)
Ying Teng, Baris Taskin
Resonant frequency divider design methodology for dynamic frequency scaling. ICCD (2013)
Ying Teng, Baris Taskin
Rotary traveling wave oscillator frequency division at nanoscale technologies. ACM Great Lakes Symposium on VLSI (2013)
Can Sitik, Baris Taskin
Multi-corner multi-voltage domain clock mesh design. ACM Great Lakes Symposium on VLSI (2013)
Vinayak Honkote, Baris Taskin
ZeROA: Zero Clock Skew Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Ying Teng, Baris Taskin
Clock mesh synthesis method using the Earth Mover's Distance under transformations. ICCD (2012)
Jianchao Lu, Ying Teng, Baris Taskin
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Jianchao Lu, Xiaomi Mao, Baris Taskin
Integrated Clock Mesh Synthesis With Incremental Register Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Can Sitik, Baris Taskin
Multi-voltage domain clock mesh design. ICCD (2012)
Ankit More, Baris Taskin
A unified design methodology for a hybrid wireless 2-D NoC. ISCAS (2012)
Ankit More, Baris Taskin
A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs. SLIP (2012)
Ying Teng, Baris Taskin
Synchronization scheme for brick-based rotary oscillator arrays. ACM Great Lakes Symposium on VLSI (2012)
Vinayak Honkote, Ankit More, Baris Taskin
3-D Parasitic Modeling for Rotary Interconnects. VLSI Design (2012)
Matthew R. Guthaus, Baris Taskin
High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD (2012)
Jianchao Lu, Xiaomi Mao, Baris Taskin
Clock mesh synthesis with gated local trees and activity driven register clustering. ICCAD (2012)
Jianchao Lu, Xiaomi Mao, Baris Taskin
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. ISPD (2011)
Shannon M. Kurtas, Baris Taskin
Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling. J. Circuits Syst. Comput. 20 (5) (2011)
Ying Teng, Jianchao Lu, Baris Taskin
ROA-brick topology for rotary resonant clocks. ICCD (2011)
Ankit More, Baris Taskin
EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. ICCD (2011)
Ying Teng, Baris Taskin
Process variation sensitivity of the Rotary Traveling Wave Oscillator. ISQED (2011)
Jianchao Lu, Baris Taskin
Clock buffer polarity assignment with skew tuning. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. DATE (2011)
Vinayak Honkote, Baris Taskin
CROA: Design and Analysis of the Custom Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Ankit More, Baris Taskin
Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip. SLIP (2011)
Jianchao Lu, Baris Taskin
Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits. ISCAS (2011)
Jianchao Lu, Baris Taskin
From RTL to GDSII: An ASIC design course development using Synopsys® University Program. MSE (2011)
Jianchao Lu, Yusuf Aksehir, Baris Taskin
Register On MEsh (ROME): A novel approach for clock mesh network synthesis. ISCAS (2011)
Ankit More, Baris Taskin
Simulation based study of wireless RF interconnects for practical CMOs implementation. SLIP (2010)
Vinayak Honkote, Baris Taskin
PEEC based parasitic modeling for power analysis on custom rotary rings. ISLPED (2010)
Ankit More, Baris Taskin
Leakage current analysis for intra-chip wireless interconnects. ISQED (2010)
Ankit More, Baris Taskin
Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. ACM Great Lakes Symposium on VLSI (2010)
Jianchao Lu, Baris Taskin
Clock buffer polarity assignment considering capacitive load. ISQED (2010)
Jianchao Lu, Baris Taskin
Clock Tree Synthesis with XOR Gates for Polarity Assignment. ISVLSI (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Baris Taskin