Savithri Sundareswaran

Publication Activity (10 Years)

Years Active: 1999-2019
Publications (10 Years): 1

Top Topics

Nearest Neighbor

Program Synthesis

Top Venues

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Tong Xu, Peng Li, Savithri Sundareswaran
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating. ACM Trans. Design Autom. Electr. Syst. 20 (3) (2015)
Savithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin
A sensitivity-aware methodology to improve cell layouts for DFM guidelines. ISQED (2011)
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
Total sensitivity based dfm optimization of standard library cells. ISPD (2010)
Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
Characterization of sequential cells for constraint sensitivities. ISQED (2009)
Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED (2008)
Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran
Faster statistical cell characterization using adjoint sensitivity analysis. CICC (2008)
Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham
A timing methodology considering within-die clock skew variations. SoCC (2008)
Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran
Transistor-Specific Delay Modeling for SSTA. DATE (2008)
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC (2007)
Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
Analyzing the risk of timing modeling based on path delay tests. ITC (2007)
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD (2007)
Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham
Small-Delay Defect Detection in the Presence of Process Variations. ISQED (2007)
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC (2006)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power supply pads and pins. DAC (2004)
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
A stochastic approach To power grid analysis. DAC (2004)
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Des. Test Comput. 20 (3) (2003)
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD (2003)
Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
Statistical delay computation considering spatial correlations. ASP-DAC (2003)
David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
Slope propagation in static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
On the interaction of power distribution network with substrate. ISLPED (2001)
David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
Slope Propagation in Static Timing Analysis. ICCAD (2000)
Savithri Sundareswaran, R. Venkatesan, S. Bhaskar
An Assertion Based Technique for Transistor Level Dynamic Power Estimation. VLSI Design (2000)
Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design (1999)