Rajendran Panda

Publication Activity (10 Years)

Years Active: 1997-2010
Publications (10 Years): 0

Publications

Preeti Ranjan Panda, Rajendran Panda
Guest Editorial: Special Issue on VLSI Design and Embedded Systems. Int. J. Parallel Program. 38 (3-4) (2010)
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
Characterization of sequential cells for constraint sensitivities. ISQED (2009)
Rajendran Panda, Preeti Ranjan Panda
"22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. J. Low Power Electron. 5 (3) (2009)
Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED (2008)
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED (2008)
Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham
A timing methodology considering within-die clock skew variations. SoCC (2008)
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD (2007)
Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
Stochastic Power Grid Analysis Considering Process Variations CoRR (2007)
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC (2007)
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD (2007)
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
Stochastic variational analysis of large power grids considering intra-die correlations. DAC (2006)
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC (2006)
Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
Pessimism reduction in crosstalk noise aware STA. ICCAD (2005)
Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
Stochastic Power Grid Analysis Considering Process Variations. DATE (2005)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
Delay noise pessimism reduction by logic correlations. ICCAD (2004)
Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
Crosstalk noise control in an SoC physical design flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED (2004)
Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
False-Noise Analysis for Domino Circuits. DATE (2004)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power supply pads and pins. DAC (2004)
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
A stochastic approach To power grid analysis. DAC (2004)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED (2003)
Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
Signal integrity management in an SoC physical design flow. ISPD (2003)
D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel
SOI Transistor Model for Fast Transient Simulation. ICCAD (2003)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-route gate sizing for crosstalk noise reduction. DAC (2003)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) (2003)
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Des. Test Comput. 20 (3) (2003)
Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
Static Electromigration Analysis for Signal Interconnects. ISQED (2003)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (1) (2003)
Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (3) (2003)
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD (2003)
Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
Statistical delay computation considering spatial correlations. ASP-DAC (2003)
Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh
Noise Injection and Propagation in High Performance Designs. ISQED (2002)
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw
circuits. IEEE Trans. Very Large Scale Integr. Syst. 10 (2) (2002)
Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj
Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED (2002)
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
Noise propagation and failure criteria for VLSI designs. ICCAD (2002)
Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda
Early probabilistic noise estimation for capacitively coupled interconnects. SLIP (2002)
Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE (2002)
Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
False-Noise Analysis Using Resolution Method. ISQED (2002)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
A precorrected-FFT method for simulating on-chip inductance. ICCAD (2002)
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
On the interaction of power distribution network with substrate. ISLPED (2001)
Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw
On-chip inductance modeling and analysis. DAC (2000)
Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw
Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design (2000)
David T. Blaauw, Rajendran Panda, Abhijit Das
Removing user specified false paths from timing graphs. DAC (2000)
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
Hierarchical analysis of power distribution networks. DAC (2000)
David T. Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
On-chip inductance modeling. ACM Great Lakes Symposium on VLSI (2000)
David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
Slope Propagation in Static Timing Analysis. ICCAD (2000)
Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards
Current signature compression for IR-drop analysis. DAC (2000)
Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
Model and analysis for combined package and on-chip power grid simulation. ISLPED (2000)
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC (1999)
Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE (1998)
Rajendran Panda, Farid N. Najm
Post-Mapping Transformations for Low-Power Synthesis. VLSI Design 1998 (3) (1998)
David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
Emerging power management tools for processor design. ISLPED (1998)
Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC (1998)
Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC (1998)
Rajendran Panda, Farid N. Najm
Technology-Dependent Transformations for Low-Power Synthesis. DAC (1997)
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
Library-less synthesis for static CMOS combinational logic circuits. ICCAD (1997)